36 PCIE-5565RC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts
Publication No. 500-9300875565-000 Rev. C.0
15
Detected Parity Error.
When set to one (1), indicates the Reflective
Memory has detected a PCI bus parity error,
even if parity error handling is disabled (the
Parity Error Response bit in the Command
register is clear).
Writing a one (1) clears this bit to zero (0)
Yes
Yes/Clr 0
Table 3-5 PCI Revision ID Register
PCI Revision ID: Offset $08
Bit
Description
Read
Write
Value after
PCI Reset
7:0
Revision ID.
Revision of board
Yes
No
Current Rev#
Table 3-6 PCI Class Code Register
PCI Class Code: Offset $09
Bit
Description
Read Write
Value
after PCI
Reset
7:0
Register Level Programming Interface.
None defined.
Yes
No
$0
15:8
Subclass Code
Yes
No
$80
23:16
Base Class Code
Yes
No
$02
Base Class Code of $02 equals Network Controller. Subclass Code of $80 equals other
network controller.
Table 3-7 PCI Cache Line Size Register
PCI Cache Line Size: Offset $0C
Bit
Description
Read Write
*Value
after PCI
Reset
7:0
System Cache Line Size.
Specified in units of 32-bit
words (8 or 16 Dwords).
Yes
Yes
$0
*
NOTE:
This register can be altered by the system BIOS during the system boot process.
Table 3-4 PCI Status Register (Continued)
PCI Status: Offset $06
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