Publication No. 500-9300527837-000 Rev. A.0
Functional Description 57
5.20 Resets and Interrupts
5.20.1 Interrupt Controllers
The PCH provides an industry standard architecture (ISA) compatible
Programmable Interrupt Controller (PIC) that incorporates the functionality of
two 82C59 interrupt controllers. These are cascaded so that 14 external and two
internal interrupts are possible. In addition, the PCH supports a serial interrupt
scheme.
The PCH also incorporates an APIC.
5.20.2 Hardware Reset
There are several methods to reset the SBC347A, and each generates one of two
reset types: a global reset (which causes the platform to enter a sleep state until
the reset source is removed) or an edge-triggered reset (which cannot be used to
hold the board in reset), and they may not result in a reset if the processor has
crashed. The table below summarizes the reset sources:
NOTE
Global type resets will result in the SBC347A entering a sleep state, so it is normal to see onboard LEDs
switching off accordingly, and it does not indicate a fault condition.
When operating as the VPX System Controller, the SBC347A asserts the VPX
SYSRESET~ signal whenever it enters a reset state.
Table 5-19 Reset Sources
Reset Source
Reset Type Comments
BIT Reset Request (FPGA register)
Edge
BIT LEDs and BIT status registers are not reset
TAC reset switch
Edge
Cannot be used to hold the board in reset
VPX SYSRESET~
(must be asserted for >10 ms)
Global
Can be used to hold the board in reset
VPX MASKABLE_RST~
(must be asserted for >10 ms)
Global
Will only cause reset if unmasked in the
Watchdog timer expired
Global
