68 SBC347A 3U VPX Single Board Computer
Publication No. 500-9300527837-000 Rev. A.0
6.22 GPIO In Register (0x671)
This returns the status of the GPIO pins, regardless of the direction mode.
6.23 GPIO Direction Register (0x672)
6.24 GPIO Interrupt Enable Register (0x673)
6.25 GPIO Level/Edge Register (0x674)
This sets the interrupt detection sensitivity of each interrupt pin (level or edge
mode):
6.26 GPIO Active Low/High Register (0x675)
This sets the interrupt detection sensitivity of each interrupt pin (active high/low
or rising/falling edge depending on the sensitivity mode):
Bits
Read/Write Description
Default
7 to 0
Read/Write GPIO7 to GPIO0 respectively
0x00
Bits
Read/Write Description
Default
7 to 0
Read/Write GPIO7 to GPIO0 respectively:
1 = Output
0 = Input
0x00
Bits
Read/Write Description
Default
7 to 0
Read/Write GPIO7 to GPIO0 respectively:
1 = Interrupt enabled
0 = Interrupt masked
0x00
Bits
Read/Write Description
Default
7 to 0
Read/Write GPIO7 to GPIO0 respectively:
1 = Edge
0 = Level
0x00
Bits
Read/Write Description
Default
7 to 0
Read/Write GPIO7 to GPIO0 respectively:
1 = Active high/rising edge
0 = Active low/falling edge
Depending on whether the bit is in level or edge mode
0x00