52 CP9*, CR9*, CT9* Celeron M/Pentium M
Publication No. HRMCP9 Rev. B
6.4 APIC Controller
The CR9 supports also the Interrupt handlings with APIC (Advanced Interrupt
Controller). This handling of the APIC interrupt services must be supported by the
operating system. The I/O APIC handles interrupts very differently than the 8259.
Briefly, these differences are:
•
Method of Interrupt Transmission. The I/O APIC transmits interrupts through a
three-wire bus, and interrupts are handled without need for the processor to run
an interrupt acknowledge cycle.
•
Interrupt Priority. The priority of interrupts in the I/O APIC is independent of
the interrupt number. For example, interrupt 10 may be given a higher priority
than interrupt 3.
•
More Interrupts. The I/O APIC in the Intel ICH4 supports a total of 24 interrupts.
For a complete operation description please refer to the ‘Intel ICH4 I/O Controller
Hub’ datasheet.