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Publication No. 500-657806-000 Rev. G
Embedded PC/RTOS Features 47
Table 3-27 Details of Preload Value 2 Register
Bit
Attribute
Description
31:20
RO
Reserved
19:0
R/W
Preload_Value_2 [19:0]: Use this register to hold the preload value
for the WDT Timer. The value in the Preload register is automatically
transferred into the 35-bit down counter every time the WDT enters
the first stage.
Note:
The value loaded into the preload register needs to be one less
than the intended period, as the timer makes use of zero based
counting (zero is counted as part of the decrement).
Note:
Please refer to the Register Unlocking Sequence section for
details on how to change the value of this register.
Table 3-28 General Interrupt Status Register
Offset
Base + 08h
Attribute
Read-Write Clear
Default Value
00h
Size
8 bit
Lockable
No
Power Well
Core
Table 3-29 Details of General Interrupt Status Register
Bit
Attribute
Description
7:1
RO
Reserved
0
R/WC
Watchdog Timer Interrupt Active: (1
st
Stage) this bit is set when
the first stage of the 35-bit Down Counter reaches 0. An interrupt
will be generated if WDT_INT_TYPE is configured to do so. See
WDT Configuration register.
This is a sticky bit and is only cleared by writing a 1.
0 - No Interrupt
1 - Interrupt Active
Note:
This bit is not set in free running mode. Use Unlock to
access.
Table 3-30 Reload Register
Offset
Base + 0Ch
Attribute
Read-Write
Default Value
0000h
Size
16 bit
Lockable
No
Power Well
Core
Table 3-31 Details of Reload Register
Bit
Attribute
Description
15:10
RO
Reserved
9
R/WC
WDT_TIMEOUT: This bit is in the RTC Well and its value is not lost when the
host resets the system. It is set to one when the host fails to reset the WDT
before the 35-bit Down Counter reaches zero for the second time in a row.
This bit is cleared by performing the Register Unlocking Sequence followed by
a 1 to this bit.
0 - Normal (Default)
1 - System has become unstable
Note:
In free running mode this bit is set every time the down counter reaches
zero.