Configuring the CBR Module
125
Figure 96 illustrates the SRTS and Adaptive timing options.
Figure 96
CBR T1-DSX Timing Options
I
dle Timer
—This parameter applies to the video dial feature. Use it to set the
length of time, in seconds (6-60) after which the CBR software shuts off cell
transmission and puts the virtual circuit into a listening mode if no cells have been
received on a T1-DSX/E1 port connected to an MCU device. If a T1-DSX/E1 port is
connected to an MCU device, the bandwidth allocated to the virtual circuits must
be saved when a video conference is not in progress. To accomplish this, the CBR
software starts an internal timer when no cell is being received. If the amount of
time you specify as the
Idle Timer
expires before another cell is received, the
software shuts off cell transmission and puts the virtual circuit into a listening
mode.
DBA Bits Mask
(Structured Data ports only)—Dynamic bandwidth allocation bits
mask; a numeric code, in the range 1-255, representing a mask that masks off bits
that are not a portion of the idle code. When a DSX-1/E-1 CBR port is configured
as structured data, all virtual circuits in the port use a preselected DBA Bits Mask.
The decimal number that represents the DBA Bits Mask corresponds to an internal
8-bit value. The default DBA Bits Mask is 127.
The
DBA Bits Mask
parameter is designed to accommodate situations in which the
PathBuilder S330/S310 must communicate with equipment that uses
non-standard signaling patterns. In most cases you should leave this parameter set
to its default value. If you are experiencing problems with a CCS circuit, however,
you may need to set the
DBA Bits Mask
to a different value. The PathBuilder
S330/S310 performance monitoring feature reports the data bytes to the cell bus
on the CBR port. You can check this statistic to determine if you need to set a
non-default DBA Bits Mask. For details, see “CBR ATM Statistics” in Chapter 5.
DS1
DS1
AAL 1
-5 Hz
Reference Check
Send Difference (-5 Hz)
Reference - 5 Hz
AAL Header
Buffer
Clock
> <
Depends
on Buffer
Adaptive
Synchronous Residual Time Stamp (SRTS)