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51
CIRCUIT
DESCRIPTION
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
ZP94/95 CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
IOO1
PSZ2
IX01
Rainforest
RGB
Processor
2H Video PWB
60
59
SCL2
SDA2
PSD2
Sweep Control
Surround PWB
Clock
Data
U205
FLEX
&
PinP
PFC1
Enable
Clock
Data
FCENAble
1
2
17
16
SCL2
SDA2
SDA2
26
27
SCL2
2
1
I201
Main Video
Chroma
33
34
SDA2
SCL2
SDA2
SCL2
U204
3DY/C
PYC1
2
3
I014
3.3V -> 5V
Level Shift
2
3
4
5
6
7
18
17
16
15
14
13
20
21
46
15
16
18
8
9
12
11
17
19
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
PSU2
5
2
6
3
1
PSU1
2
1
IS03
Front
Audio
Control
SCL2
SDA
2
IS08
Center/LFE/
PinP
Audio Control
IS10
Center
Equalizer
IS05
Front
Equalizer
SCL2
SDA2
SCL2
SDA2
IS01
DAC3
SCL2
SDA2
I403
Sub
Video
Chroma
PST1
Deflection PWB
Signal PWB
I701
9
12
8
11
13
DSP
Unit
HC4051
PMU1
5
6
I401
A/V Select
SCL1
34
33
SDA
1
FCEN
SCL2
SDA2
SCL2
SDA2
10
11
12
4
5
4
5
17
16
17
16
14
15
3
2
SCL1
SDA1
IOO2
EEPROM
5
6
SDA1
SCL1
I004
DAC2
SDA1
SCL1
5
6
5
6
SDA1
SCL1
I003
DAC1
SCL3
SDA3
58
57
SCL3
IS11
Rear
Audio Control
SDA3
Terminal PWB
3
4
5
4
DSPSS
DSPSCK
DSPERR Mute
DSPI
DSPRST
FEENABLE2
43
17
U202
Tuner 2
Pinp
16
Clock
Data
15
Enable
6
Enable
U201
Tuner 1
Main
FEENABLE1
44
5
Clock
Data
4
33
34
SDA2
SCL2
2
1