6-4
IM DLM6054-17EN
6.3 Standard Event Register
Standard Event Registr
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYERQCOPC
• Bit 7 PON (Power ON)
Set to 1 when the power is turned ON.
• Bit 6 URQ (User Request)
Not used (always 0)
• Bit 5 CME (Command Error)
Set to 1 when the command syntax is incorrect.
Example Incorrectly spelled command name; “9”
used in octal data.
• Bit 4 EXE (Execution Error)
Set to 1 when the command syntax is correct but
the command cannot be executed in the current
state.
Example Received a command with a parameter
outside the range or attempted to output
a hard copy while waveform acquisition
is in progress.
• Bit 3 DDE (Device Dependent Error)
Set to 1 when execution of the command is not
possible due to an internal problem in the instrument
that is not a command error or an execution error.
• Bit 2 QYE (Query Error)
Set to 1 if the output queue is empty or if the data is
missing even after a query has been sent.
Example No response data; data is lost due to an
overflow in the output queue.
• Bit 1 RQC (Request Control)
Not used (always 0)
• Bit 0 OPC (Operation Complete)
Set to 1 when the operation designated by the *OPC
command (see chapter 5) has been completed.
Bit Masking
To mask a bit in the standard event register so that
it does not cause bit 5 (ESB) of the status byte to
change, set the corresponding bit in the standard event
enable register to 0. Refer to Chapter 4.
For example, to mask bit 2 (QYE) so that ESB will not
be set to 1, even if a query error occurs, set bit 2 of the
standard event enable register to 0. This can be done
using the *ESE command. To inquire whether each
bit of the standard event enable register is 1 or 0, use
the *ESE?. For details on the *ESE command, see
chapter 5.
Operation of the Standard Event Register
The standard event register is provided for eight
different kinds of event which can occur inside the
instrument. Bit 5 (ESB) of the status byte is set to 1
when any of the bits in this register becomes 1 (or
when the corresponding bit of the standard event
enable register becomes 1).
Example
1. A query error occurs.
2. Bit 2 (QYE) is set to 1.
3. Bit 5 (ESB) of the status byte is set to 1 if bit 2 of the
standard event enable register is 1.
It is also possible to check what type of event has
occurred inside the instrument by reading the contents
of the standard event register.
Reading from the Standard Event Register
The contents of the standard event register can be
read by the *ESR command. After the register is read,
it is cleared.
Clearing the Standard Event Register
The standard event register is cleared in the following
three cases.
• When the contents of the standard event register
are read using the *ESR command.
• When a *CLS command is received.
• When the instrument is power cycled.
