Yamaha YSP-4100, Руководство по обслуживанию

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62
YSP-4100/YSP-5100
Y
SP-41
0
0/Y
SP-51
0
0
Pin
No.
Port
Name
Control Interrupt Timer UART Analog
Function
Name
I/O Detail of Function
1 P96
TxD4/
SDA4/
SRxD4
ANEX1 AW_MOSI S-OUT Air-Wired (1, 2) SPI data OUT (iPod asynchronous data output)
2 P95 CLK4 ANEX0 AW_SCK S-CLK Air-Wired (1, 2) SPI clock OUT
3 P94 TB4IN
CTS4/
RTS4/SS4
DA1
AW_N_
INT1
TMR-IN Air-Wired 1 interrupt IN (Reception)
4 P93 TB3IN
CTS3/
RTS3/SS3
DA0
AW_N_
INT2
OUT
5 P92 TB2IN
TxD3/
SDA3/
SRxD3
RDS_N_
RDY/SR_
MOSI
Tx/
TMR-IN
Sirius/XM asynchronous data output (U, C models)
RDS READY input (G models)
[RDS: Pull-up resistor required]
6 P91 TB1IN
RxD3/
SCL3/
STxD3
RDS_
MISO/
SR_MISO
Rx/S-IN
Sirius/XM asynchronous data input (U, C models)
RDS synchronous data input (G models)
[Sirius: Pulled up by 100k-ohms]
7 P90 TB0IN CLK3 RDS_SCK
IN/
S-CLK
RDS synchronous clock output (G models)
CXM LINK detection (U, C models)
8 P146 INT8
INT_N_
PWMAMP
INT-IN
iPod detection
[H changed to L with iPod inserted into dock]
[Pull-up resistor required]
9 P145 INT7
DIR_N_
INT
INT-IN DIR interrupt
10 P144 INT6
DSP1_N_
INT
INT-IN DA70Y (former stage) interrupt
11 P143
RDS_N_
RST
OUT
RDS reset (G models)
XM reset (U, C models)
12 P142
CDDA-
DATA
IN
DIR DATA input when in CDDA writing mode
XM antenna revision detection (U, C models)
[H: incompatible antenna]
13 P141
DIR_N_
CS
OUT DIR chip selection
14 P140
DSP1_N_
RST
OUT DA 70Y (former stage) reset
15 BYTE BYTE --- When in Single chip mode: Vss (GND)
16 CNVSS CNVss ---
Processor mode selection: Lo: Single chip mode
Hi: to FLASH included boot mode
To boot mode with P50=H, P55=L, CNVss=H settings when resetting hardware
*
Pull down required
17 P87 XCIN
DSP1_N_
CS
OUT DA70Y (former stage) chip select
18 P86 XCOUT SR_PON OUT
SIRIUS
XM radio power supply ON/OFF control DAC chip select RESET
[H: Power ON L: Power OFF]
19 RESET N_RESET ---
RESET
[L: RESET]
20 XOUT Xout --- 20MHz OUT
21 VSS Vss --- GND
22 XIN Xin --- 20MHz IN
23 VCC1 Vcc1 --- Power 3.3V
24 P85 NMI NMI IN Connect to Vcc via resistor
25 P84 INT2
HDMI_
MUTE
INT-IN
HDMI MUTE input
[H: Mute]
26 P83 INT1 HDMI_INT INT-IN Interrupt from HDMI RX
27 P82 INT0 CEC_INT INT-IN CEC microprocessor interrupt
28 P81
TA4IN/U/
RTP23
CTS5/
RTS5
CDDA_
WCK
IN DIR_WCK input for CDDA writing
29 P80
TA4OUT/
U
RxD5
DSP_
MISO
S-IN DIR, DA70Y (former stage / latter stage), DAC synchronous data input
30 P77
TA3IN/
RTP22
CLK5 DSP_SCK S-CLK DIR, DA70Y (former stage / latter stage), DAC synchronous clock output
31 P76 TA3OUT TxD5
DSP_
MOSI
S-OUT DIR, DA70Y (former stage / latter stage), DAC synchronous data output
32 P75
TA2IN/W/
RTP21
DIR_N_
RST
OUT DIR reset
33 P74
TA2OUT/
W/RTP20
FL_78.4K TMR-OUT For FL filament (78.4KHz/PWM)
34 P73 TA1IN/V
CTS2/
RTS2/SS2
232C_
MISO
TMR-IN
RS232C reception detection
Connect to 40 pin
35 P72
TA1OUT/
V
CLK2
DSP1_N_
READY
IN
DA70Y (former stage) RDY CDDA writing path selection
[H: CDDA writing mode L: Normal operation mode]
36 P71
TB5IN/
TA0IN/
RTP03
RxD2/
SCL2/
STxD2
SCL_100 SCL
I2C SCL output (100kHz device)
[Pull-up resistor required N-OD]