Yamaha YSP-4100, Руководство по обслуживанию

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A
1 2 3 4 5 6 7 8 9
10
BCD
E
F
G
H
I
J
K
L
M
N
YSP-4100/YSP-5100
100
HDMI 2/2
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
●
電圧は、内部抵抗
10MΩの電圧計で測定したものです。
●
⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、 パーツリストに記載されている部品を使用してください。
●
本回路図は標準回路図です。改良のため予告なく変更することがございます。
IC302
IC303
IC304 IC305
IC301
IC306
CB302
IC9 IC10 IC8
CB301
CB413
0 0 0 0 0 0 0 0 0
0 0
0 0
0.5
0
0
0
0
0
0
0
0
0
3.4
0 3.4 1.8 0
1.6 2.0
0
3.4 0.9 1.9 1.2
0
0.3
0
1.7
0 0 0 0 0 0 0 0
2.5 2.5
0 0 0 0
1.8 0 3.3 2.5 3.1 1.7 0 3.4 0.9 0.7
0 0 0 0
0 0
0 0 0 0
0.7
1.8
1.0
0
1.9
3.3
0
1.6
1.5
3.4
0
0
1.8
0
0
0
0
0
0
0
0
0
0
3.4
1.8
0
0
0
0
0
0
0
0
0
0
0
0
3.4
0
0
0
0
1.8
0
0
0
0
0
3.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.9
1.8
0
1.6
1.4
1.3
1.1
1.1
1.4
3.4
0
0
3.4
0
0
0
0
1.8
0
3.4
0 0 0 0 0 0 0 0
3.4
0 0 0
1.9 1.6 1.4 1.3 1.1
0
3.4 1.7
0 0
1.1 1.4 2.5 3.3 3.3
0
3.4
0 0 0 0 1.9 1.6 1.3 1.7 1.3 0 0 0 0 0 1.3 2.2 2.5 3.3 3.3 0 0 0 0 0 0 1.6 0 0 0 0
3.4 0
3.9
1.9
3.4
3.9
3.9
3.9 0
0
1.8
1.8
1.8
0
2.3
2.3
2.3 0
1.2
1.2
6.6
0
3.9 2.3 2.3
0 0
1.2
0
2.3
2.3
3.0
2.3
2.3
2.3 0
0
1.9
1.9
3.4
3.4
0
0
J
POINT
J XL30
1 (Pin 81 of IC30
1)
INPUT MUX
OUTPUT FIFO AND FORMATTER
IC30
1
: AD
V7800BS
TZ-80
1
0-bit, SDTV/HDTV 3D comb f
ilt
er
, video decoder and g
raphics digitiz
er
CLAMP
12
ANTIALIAS
FILTER
ADC
24
P30 TO P53
GRAPHICS RGB
AIN1
AIN12 CVBS
S-VIDEO
SCART-
(CBVS+RGB)
YPrPb
TO
CVBS OUT
FB
HS_IN2 VS_IN2
HS_IN VS_IN
SOG SOY
SCLK
SCLK2
SDA
SDA2 ALSB
INT
CLK_IN
DE_IN
10
CLAMP
ANTIALIAS
FILTER
ADC
10
CLAMP
ANTIALIAS
FILTER
ADC
10
2D COMB
CLAMP
DIGITAL INPUT PORT
DVI OR HDMI
SYNC PROCESSING AND
CLOCK GENERATION
SERIAL INTERFACE
CONTROL AND VBI DATA
COLORSPACE CONVERSION
SSPD
STDI
ANTIALIAS
FILTER
ADC
10
10 10 10 10
DAC
CORE
CLK
COMPONENT PROCESSOR (CP)
STANDARD DEFINITION PROCESSOR (SDP)
DDR/SDR-SDRAM INTERFACE
DDR/SDR-SDRAM INTERFACE
VBI DATA PROCESSOR (VDP)
GAIN
CONTROL
MACROVISION
DETECTION
ACTIVE PEAK
AND AGC
DIGITAL
FINE
CLAMP
AV CODE
INSERTION
OFFSET
CONTROL
LLC SFL/SYNC_OUT FIELD/DE VS CS/HS PIXEL DATA P0 TO P53
AV CODE
INSERTION FAST BLANK
OVERLAY CONTROL
VERTICAL
PEAKING
MACROVISION
DETECTION
HORIZONTAL
PEAKING
CTI LTI
ITOP
STANDARD
AUTODECTION COLORSPACE
CONVERSION
525p/625p SUPPORT
3D COMB
TBC
MUX
54
IC303
: R1
1
72H1
81B-T1
-F
V
olt
age r
egulat
or
V
DD CE
Pin No
.
1 2 3 4 5
S
ymbol
CE
GND
NC
V
DD
V
OUT
Descr
iption
Chip Enab
le Pin
Gr
ound Pin
No C
onnection
Input Pin Output Pin of
V
olt
age R
egulat
or
Vr
ef
45 12
Curr
ent Limit
V
OUT
GND
V
DD CE
Pin No
.
1 2 3 4 5
S
ymbol
CE
GND
NC V
DD
V
OUT
Descr
iption
Chip Enab
le Pin
Gr
ound Pin
No C
onnection
Input Pin Output Pin of
V
olt
age R
egulat
or
Vr
ef
45 12
Curr
ent Limit
V
OUT
GND
IC302
: R1
1
72H331D-T1
-F
V
olt
age r
egulat
or
IC305
: R1
1
72S1
81B-E2-F
V
olt
age r
egulat
or
V
DD CE
Pin No
.
1
2, 5
3 4 6
S
ymbol V
OUT
GND
CE NC
V
DD
Descr
iption
Output Pin of
V
olt
age R
egulat
or
Gr
ound Pin
Chip Enab
le Pin
No C
onnection
Input Pin
Vr
ef
61 3
2,5
Curr
ent Limit
V
OUT
GND
V
DD CE
Pin No
.
1
2, 5
3 4 6
S
ymbol V
OUT
GND
CE NC V
DD
Descr
iption
Output Pin of
V
olt
age R
egulat
or
Gr
ound Pin
Chip Enab
le Pin
No C
onnection
Input Pin
Vr
ef
61 3
2,5
Curr
ent Limit
V
OUT
GND
IC304
: R1
1
72S331B-E2-F
CMOS-based positiv
e-v
olt
age r
egulat
or IC
1
DIR
A1 A2 A3 A4 A5 A6 A7 A8
GND
Vcc OE B1 B2 B3 B4 B5 B6 B7 B8
2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
IC8-10
: SN74LVC245APWR
Octal bus transceivers with 3-state outputs
To HDMI 1/2
To HDMI 1/2
VIDEO DECODER
to POWER (1)_W508
P
age 97
K8
to DSP_W403
P
age 91
C1
to DSP_W413
P
age 91
C1