Yamaha dsp-ax3800, Руководство по обслуживанию

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2
A B C D E F G H I J
1
3
4
5
7
RX-V3800/DSP-AX3800
6
90
NETWORK SECTION BLOCK DIAGRAM
D[0]~D[15] D[0]~D[15]
A[1]~A[21] A[0]~A[11],A[14],A[15]
<Power>
Reset for FLASH
Serial communication
Between EP9301 and iPod (UART0)
Serial communication
Between EP9301 and main microprocessor
(UART1)
Reset from main microprocessor to P.C.B. NET
Reset for EP9301
USB power enable
Error detect
<USB2.0 HOST(Full Speed)>
NETWORK
BICK
LRCK
SDO(I2S)
IC752 NJM4565M
MUTE
(*1) +2.5A is generated by IC701 itself.
Full/Half DUPLEX
DAC for VCXO
BH2220FVM
IC754
(+3.3D)
LOGIC for AUDIO CLOCK
SN74LV163APWR IC615,616
SN74LV74APWR IC617
(+3.3D)
AUDIO
DAC
PCM1781DBQR
IC751
(+5A)
[MII I/F]
3.3V 5V
74LCX07MTCX
IC614
(+3.3D)
128Mbit SDRAM
EDS1216AATA-75
IC611
(+3.3D)
32Mbit FLASH-ROM
S29JL032H70TFI020
IC613
(+3.3D)
MICROPROCESSOR
(NET)
EP9301-CQZ
[166MHz]
IC610
(RVDD:+3.3DC)
(CVDD:+1.8DC)
+3.3D
PHYceiver
KSZ8721SL
IC701
(+3.3D)
(+2.5A)(*1)
25MHz
XL701
100M/10M
Reset
Power down
22.5792MHz
+3.3DC
22.5792MHz
VCXO
XL751
REGULATOR
PQ018EZ01ZPH
IC604
(3.3V → 1.8V)
14.7456MHz
XL602
32.768KHz
XL601
POWER DISTRIBUTION
SWITCH for USB
MIC2026-2YM
IC609
Control
Voltage
+1.8DC
RESET CIRCUIT
Power on reset
BD4830FVE-TR
IC601
SDCLK=66MHz SDCLK=66MHz
+3.3D(700mA)
+5D (520mA)
+12A(50mA)
+5U for USB(500mA)
+5D
DA** AD** CLK CKE DQMU DQML /WE /CAS /RAS /CS
SDCLK
SDCLKEN
DQMn[1]
DQMn[0]
SDWEn
CASn
RASn
SDCSn[3]
10
208
23
24
14
22
21
15
38 37 39 15 16 17 18 19
DQ**
A**
DQ**
A**
/RESET
/CE /WE /OE
CSn[6]
WRn
RDn
2
194
193
26 11 28
RXD[0]
TXD[0]
RXD[1]
TXD[1]
109
113
110
114
PRSTn
125
12
W605
1
2
3
1:+3.3_N
2:NETG
3:+5_N
CB601 CB408
6
5
3
2
1
4
11
8
5
10
9
6
1:RXDi(3.3V)
2:TXDi(3.3V)
4:TXDNW(5V)
5:RXDNW(5V)
6:NW_RST
3:MG
CB603
W3102
1:VBus
2:-DATA
3:+DATA
4:GND
5:FG
8
7
1
2
1
2
3
4
5
USB
W751
CB562
4:+12
1:NETL
3:NETR
2:E
4
2
EGPIO[4]
147
EGPIO[3]
148
USBm[2]
USBp[2]
157
158
FGPIO[3]
FGPIO[2]
FGPIO[1]
CLK
DI
LD
7
6
8
AO1
1
168
169
170
93
94
96
146 7
8
6
4
5
DGND
DACGND
1
3
+12A
DACGND
15(Lch)
14(Rch)
(RVDD)
(CVDD)
1,2
3
SCLK
LRCK
SDO0
EGPIO[5]
EGPIO[9]
EGPIO[10]
142
141
SPD100
DUPLEX
27
28
EGPIO[6]
EGPIO[7]
145
144
48
30
/RST
/PD
TX+,TX-
RX+,RX-
41,40
33,32 1,3
4,6
DGND
DGND
XTALI
XTALO
118
119
RTCXTALI
137
XI
XO
46
45
DACGND
+5A
11
CB701
MDC,MDIO
RXD[3:0],RXDVAL,RXCLK,RXERR
TXD[3:0],TXEN,TXCLK,TXERR
CRS,CLD
CB531
FUNCTION
• See page 126-129
→
SCHEMATIC DIAGRAM
DSP
• See page 123-125
→
SCHEMATIC DIAGRAM
NET
• See page 142, 143
→
SCHEMATIC DIAGRAM
DSP
• See page 123-125
→
SCHEMATIC DIAGRAM
OPERATION
• See page 130
→
SCHEMATIC DIAGRAM