Yamaha dsp-ax3800, Руководство по обслуживанию

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81
RX-V3800/DSP-AX3800
RX-V3800/
DSP-AX3800
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102
103
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105
106
107
108
109
110
EM_D[14]
CVDD
EM_D[13]
EM_D[12]
DVDD
EM_D[11]
VSS
EM_D[10]
EM_D[9]
CVDD
EM_D[8]
EM_WE_DQM[1]
DVDD
VSS
EM_CLK
EM_CKE
VSS
DVDD
EM_A[11]
EM_A[9]
EM_A[8]
CVDD
VSS
EM_A[7]
EM_A[6]
DVDD
VSS
EM_A[5]
EM_A[4]
CVDD
EM_A[3]
VSS
EM_A[2]
EM_A[1]
CVDD
EM_A[0]
DVDD
EM_A[10]
EM_BA[1]
VSS
EM_BA[0]
EM_CS[0]
EM_RAS
VSS
EM_CS[2]
CVDD
NC
DVDD
EM_OE
SPI0_ENA/I2C1_SDA
VSS
SPI0_ENA/I2C1_SCL
SPI0_CLK/I2C0_SCL
VSS
SPIO_SIMO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
IO
IO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-Bits]
EMIF data bus [lower 16-bits]
Write enable or byte enable for EM_D [15:8]
SDRAM clock
SDRAM clock enable
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
EMIF address bus
SDRAM bank address and asynchronous memory Low-Order address
SDRAM bank address and asynchronous memory Low-Order address
SDRAM chip select
SDRAM row address strobe
Asynchronous memory chip Select
Asynchronous memory read/not write
SDRAM output enable
SPI0 enable (ready) or I2c1 serial data
SPI0 enable (ready) or I2c1 serial clock
SPI0 serial clock or I2c0 serial clock
SPI0 data pin slave in master out
NO. Function Name (P.C.B.) TYPE (1) PULL (2) GPIO (3) Detail of Function