Yamaha dsp-ax3800, Руководство по обслуживанию

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RX-V3800/DSP-AX3800
RX-V3800/
DSP-AX3800
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SPIO_SOMI/I2C0_SDA
DVDD
AXR0[0]
VSS
AXR0[1]
AXR0[2]
AXR0[3]
VSS
AXR0[4]
SPI1_SCS
SPI1_ENA
SPI1_CLK
CVDD
VSS
DVDD
/SPI1_SOMI
/SPI1_SIMO
CVDD
VSS
AXR0[10]
AXR0[11]
CVDD
VSS
AXR0[12]
AXR0[13]
DVDD
AXR0[14]
AXR0[15]
ACLKR0
VSS
AFSR0
ACLKX0
AHCLKR0/AHCLKR1
AFSX0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SPI0 data pin slave out master in or I2C0 serial data
McASP0 serial data 0
McASP0 serial data 1
McASP0 serial data 2
McASP0 serial data 3
McASP0 serial data 4
McASP0 serial data 5 or SPI1 slave chip select
McASP0 serial data 6 or SPI1 enable (ready)
McASP0 serial data 7 or SPI1 serial clock
McASP0 serial data 8 or McASP1 serial data 5 or SPI1 data pin slave out
master in
McASP0 serial data 9 or McASP1 serial data 4 or SPI1 data pin slave in
master out
McASP0 serial data 10 or McASP1 serial data 3
McASP0 serial data 11 or McASP1 serial data 2
McASP0 serial data 12 or McASP1 serial data 1
McASP0 serial data 13 or McASP1 serial data 0
McASP0 serial data 14 or McASP2 serial data 1
McASP0 serial data 15 or McASP2 serial data 0
McASP0 receive bit clock
McASP0 receive frame Sync (L/R clock)
McASP0 transmit bit clock
McASP0 and McASP1 receive master clock
McASP0 transmit frame Sync (L/R clock)
NO. Function Name (P.C.B.) TYPE (1) PULL (2) GPIO (3) Detail of Function