Xycom XVME-400, Руководство пользователя

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XVME-400/401/490/491 Manual
October, 1989
3.5 SERIAL CHANNEL CLOCK CONFIGURATIONS
The receiver and/or transmitter can be independently programmed to accept their clock
source from any of the following: the RXC/RT signal, the baud rate generator, or the
digital phase locked loop (see the SCC manual). (TXC/TT may not be programmed as a
clock source.)
The receiver option is specified in WRl l:D6,D5, the transmitter in
WRl l:D4, D3.
The TXC/TT output signal may be programmed to output any of the following: the baud
rate generator, the digital phase lock loop, or the transmitter’s clock. This is selected via
WRl l:Dl, DO.
Any combination of clock rate and baud rate options may be used in synchronous or
asynchronous modes. Four typical examples are given below:
1)
2)
3)
4)
36 .
Asvnchronous Operation
The baud rate generator is used as the transmitter and receiver clocks. The master
clock signal received on the pin PCLK is used for the generator’s input. The external
clock’s RXC/RT and TXC/TT are not used.
Svnchronous Operation. External Transmitter and Receiver Timing Definition
The RXC/RT clock input is used for the transmitter and receiver clocks. TXC/SD
output will be synchronized to the clock input on RXC/RT. RXD/RT input will be
sampled by clock input RXC/RT. The baud rate generator is not used.
Svnchronous Operation. Internal Transmitter and Receiver Timing Definition
The baud rate generator is used for the transmitter and receiver clocks. TXC/TT
output signal is programmed to output the baud rate generator. TXC/SD output will
be synchronized to the clock output TXC/TT. RXD/RD input will be sampled by
clock output TXC/TT.
Svnchronous Operation. External Receiver Timing Definition and Internal
Transmitter Timing Definition
The baud rate generator is used for the transmitter clock and is sent out on the
TXC/TT line. The RXC/RT signal is used for the receiver clock. TXD/SD output
will be synchronized to the clock output TXC/TT. RXD/RD input will be sampled
by clock input RXC/RT.
MODULE RESET OPERATION
The module is reset by the assertion of VMEbus signal SYSRESET*. In response, the
module will reset its VMEbus interface and the SCCs. Refer to the SCC technical manual
for SCC reset operation.
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