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XVME-400/40 l/490/49 1 Manual
October, 1989

Table A-2. Pl Signal Identification

Number

5
6
7
8
9

10
1 1
12
13
14
15

16
17
I8
19

20
21
22
23
24
25
26
27
28
29
30
31
32

Row A

Signal

Mnemonic

D00
DO1
D O 2
D O 3
D O 4
D O 5
D O 6
D O 7

G N D
SYSCLK
G N D
DSl*
DSO*
WRITE*
G N D
DTACK*
G N D
AS*
G N D
I A C K *
IACKIN*

IACKOUT*

AM4
A07
A06
A05
A04
A03
A02

A01

-12v
+5v

Row B Row C

Signal

Mnemonic

BBSY*

D O 8

BCLR*

D O 9

ACFAIL*

Dl0

BG0IN*

Dll

BGOOUT* D12
BGlIN*

D13

BGlOUT”

D14

BG2IN*

D15

BG2OUT*

G N D

BG3IN* SYSFAIL*
BG30UT* BERR*
BR0* SYSRESET*
B R l * LWORD*
BR2*

AM5

BR3*

A23

AM0

A22

AM1

A21

A M 2

A20

AM3

A19

G N D

A l 8

SERCLK( 1)

A l 7

SERDAT( 1)

A l 6

G N D

A l 5

IRQ7*

A l 4

IRQ6*

A l 3

IRQ5”

A l 2

IRQ4*

A l l

IRQ3*

A10

IRQ2*

A09

IRQl*

A08

+5V STDBY

+12v

+5v

A-6

Содержание XVME-400

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Страница 6: ...asynchronous byte synchronous and bit oriented protocols Each channel is independently programmable and has its own baud rate generator The VMEbus interface directly maps the SCC chips into the short...

Страница 7: ...requirements Appendix A VMEbus connector and pin descriptions Appendix B Quick reference guide with jumper configurations Appendix C Block diagrams assembly drawings and schematics NOTE This manual XY...

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Страница 10: ...nal sync Modem Control Signals Available XVME 400 40 l 490 XVME 491 Specification 4 Zilog 28530 RS 232C RS 485 422A 57 6 Kbytes 500 Kbytes 57 6 Kbytes 500 Kbytes RTS CTS DCD DTR RTS CTS DCD Power Requ...

Страница 11: ...g peak acceleration 11 msec duration 50 g peak acceleration 11 msec duration VMEbus Compliance Complies with VMEbus Specification IEEE 1014 A16 D8 0 DTB Slave Interrupt vector D08 0 DYN I 1 to I 7 int...

Страница 12: ...inimum system requirements for the operation of an XVME 400 401 490 491 Module are one of the following A A host processor properly installed on the same backplane A properly installed system controll...

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Страница 17: ...JKl and JK2 respectively XVME 401 only refer to Section 2 4 4 J3 J6 J7 Allows tri stating of any of the channels refer to Section 2 4 5 Determines whether the module will respond to supervisory or su...

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Страница 19: ...d J7 XVME 401 491 In 2DH Supervisory only Out 2DH Supervisory or 29H Non privileged 2 4 3 Interrupt Level Selection Jumpers JAl JA3 The XVME 400 401 490 491 Module can either be configured to generate...

Страница 20: ...umper to determine how the RTS output affects line driver enabling When a channel s jumper is in the A position the line drivers associated with that channel for TT RS SD and TR will be controlled by...

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Страница 22: ...e slash and the RS 485 422A signal names to the right XVME 40l 491 All line drivers invert the signal For modem control lines writing a 1 to the appropriate SCC writer register bit will cause the outp...

Страница 23: ...RXD3 Receive Data I N RTS2 RTS3 Request To Send O U T RXC2 Ch 2 RXC3 Ch 3 Receiving Clock I N CTS2 CTS3 Clear To Send I N GND GND Ground DTR2 DTR3 Data Terminal Ready OUT DCD2 DCD3 Data Carrier Detect...

Страница 24: ...Ready OUT 17 TROA TRlA Data Terminal Ready OUT 18 RROB RRlB Data Carrier Detect I N 19 RROA RRlA Data Carrier Detect I N 20 TTOB TTlB Transmit Clock OUT 21 TTOA TTlA Transmit Clock OUT 24 SC0 SC1 Log...

Страница 25: ...Ebus defined NEXP modules The signal definitions and pin outs for connector Pl are found in Appendix A of this manual The PI connector is designed to mechanically interface with a VMEbus defined P 1 b...

Страница 26: ...XD3 27 RTS3 28 RXC3 Ch 3 29 CTS3 30 DTR3 31 DCD3 32 TXC3 Row B Signal NC NC NC NC NC GND NC NC NC NC NC NC NC NC GND v c c Row C Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND...

Страница 27: ...O v c c TXDO TXCO GND TXCO RTSO NC RTSO RXDO Ch 0 NC RXDO RXCO NC RXCO CTSO NC CTSO DCDO NC DCDO GND NC GND TXDl NC TXDI TXCl NC TXCl RTSl NC RTSl RXDl Ch 1 GND RXDl RXCl v c c RXCl CTSl NC I CTSl DCD...

Страница 28: ...in the cardcage perform the following steps 1 Make certain that the particular cardcage slot which you are going to use is clear and accessible 2 Center the board on the plastic guides in the slot so...

Страница 29: ...ving the lowest priority Therefore for a given application the serial links running at higher data rates should be assigned to module channels with higher interrupt priority 3 2 MODULE ADDRESSING The...

Страница 30: ...ter Serial Channel 2 Control Register Serial Channel 2 Data Register Serial Channel 1 Control Register Serial Channel 1 Data Register Serial Channel 0 Control Register Serial Channel 0 Data Register S...

Страница 31: ...Transmit Buffer Empty 1 External Status Change 2 Receive Character Available 2 Transmit Buffer Empty 2 External Status Change 3 Receive Character Available 3 Transmit Buffer Empty 3 External Status C...

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Страница 33: ...quence should be executed in the specified order i 1 Read RR1 to determine the source of special condition 2 Issue reset error command in WRO to clear errors 3 Read the data register 3 3 2 Transmit Bu...

Страница 34: ...RXC RT in this section The crystal oscillator feature of the SCC is not used The SCC transmit clock pin TRXC is used as an output It is buffered by line drivers and driven to a TXC TT output on a fro...

Страница 35: ...Constant 2 In the above equations CM is the clock multiplier used by the transmitter and receiver i e CM 1 6 for X 16 clock multiplier The output of the baud rate generator can be used as the transmi...

Страница 36: ...Time Constant I WR13 Value Base 10 Hex 00 16 00 2E 00 5E 00 BE 00 FE 01 7E 01 FE 02 FE 03 FE 05 FE OB FE 17 FE WR12 Value Hex Table 3 5 Typical Time Constraints for Asynchronous x16 Clock Baud Rate 1...

Страница 37: ...onous Operation External Transmitter and Receiver Timing Definition The RXC RT clock input is used for the transmitter and receiver clocks TXC SD output will be synchronized to the clock input on RXC...

Страница 38: ...r D4 D3 Set D2 to 1 to select the TRXC pin as an output WR14 Set D2 to 0 to program the DTR REQ pin to the DTR function 3 7 1 Asynchronous Operation Initialization This section describes the steps req...

Страница 39: ...D2 0 0 parity odd even enable in D1 DO 3 Set WRI0 as required 4 Set WR6 and WR7 to the sync character or SDLC address as required 5 Set WR3 as follows number of receive bits character in D7 D6 D5 D4 D...

Страница 40: ...t of stack SCC l control register Load stack pointer Load status register Configure cha nnel A of SCC l LEA L SCClAC AO M0VE W 000A D7 Load address of module 9600 baud time constant BSR S ASYNC INIT I...

Страница 41: ...M0VE B M0VE B 9 A0 Set WR9 8O AO Reset channe 1 A SCC l 4 A0 Set WR4 X16 clock 1 stop bit 01000101 A0 Odd parity enabled 3 A0 11000000 A0 5 A0 ll lOOOlO AO l AO 01000100 A0 2 A0 4O AO 9 A0 00001001 A...

Страница 42: ...nal interrupts Enable receiver Enable transmitter RTS I This routine will transmit a byte in polled mode On entry A2 contains the address of the command register of the SCC channel used for transmitti...

Страница 43: ...egister of the SCC channel used for receiving On exit D3 B contains the byte which was received RPOLA M0VE M L DO D 1 A 1 SP RXPOLL M0VE B A3 DO BTST O DO BEQ S RXPOLL RXCHA M0VE B 2 A3 D3 Save regist...

Страница 44: ...auto enables DTR TR and RTS RS asserted Receive clock transmit clock and TXC TT programed for BRG Output BRG clock PCLK ASYNC INIT M0VE B 4 A0 M0VE B 01000101 A0 M0VE B M0VE B M0VE B M0VE B M0VE B M0...

Страница 45: ...M0VE B 12 AO M0VE B D7 AO Set WR12 Low Order Time constant M0VE B 14 A0 M0VE B 2 A0 M0VE B 14 A0 M0VE B 3 A0 Set WR14 BRG source PCLK Enable BRG M0VE B 15 A0 Set WR15 Disable all external M0VE B 0 A0...

Страница 46: ...19 C 14 Signal Name and Description AC FAILURE Open collector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels...

Страница 47: ...ndicate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collecto...

Страница 48: ...ate driven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word t...

Страница 49: ...chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal...

Страница 50: ...collector driven signal which when low will cause the system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or write A hig...

Страница 51: ...WRITE GND DTACK GND AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A03 A02 A01 12v 5v Row B Row C Signal Signal Mnemonic Mnemonic BBSY DO8 BCLR DO9 ACFAIL Dl0 BG0IN Dll BGOOUT D12 BGlIN D13 BGlOUT D14...

Страница 52: ...25 26 27 28 29 30 31 32 Row A Signal Row B Signal Row C Signal TXDO v c c GND RXDO GND GND RTSO NC GND RXCO Ch 0 NC GND CTSO NC GND DTRO NC GND DCDO NC GND TXCO NC GND TXDl NC GND RXDl NC GND RTSl NC...

Страница 53: ...15 DCDl 16 GND 17 TXD2 18 TXC2 19 RTS2 20 RXD2 Ch 2 21 RXC2 22 CTS2 23 DCD2 24 GND 25 TXD3 26 TXC3 27 RTS3 28 RXD3 Ch 3 29 RXC3 30 CTS3 31 DCD3 32 GND NC TXDl NC TXCl NC RTSI GND RXDl v c c RXCl NC CT...

Страница 54: ...l Data Carrier Detected IN TXCO TXCl Transmitting Clock OUT TXD2 TXD3 Transmit Data OUT RXD2 RXD3 Receive Data I N RTS2 RTS3 Request To Send OUT RXC2 Ch 2 RXC3 Ch 3 Receiving Clock I N CTS2 CTS3 Clear...

Страница 55: ...und GND 2 5 S G O SGl Logic Ground GND 26 SD2B SD3B Transmit Data OUT 27 SD2A SD3A Transmit Data OUT 30 RD2B RD3B Receive Data I N 31 RD2A RD3A Receive Data I N 32 RS2B RS3B Request To Send OUT 33 RS2...

Страница 56: ...to this pin DTR TR SCC output pin DTR drives a line driver Driver output is sent to this pin Destinations of JK 1 JK2 or P2 Connector Input Signals one set for each serial channel RXD RD This input p...

Страница 57: ...rupt level for the module refer to Section 2 4 3 of this manual Table B 2 XVME 401 and XVME 491 Jumper List Jumper Jl and J2 Use Bring the 5V supply to front edge connectors JKl and JK2 respectively X...

Страница 58: ...Level Jumper Positions JA3 In In In In out out out out JA2 In In out out In In out out JAI In out In out In out In out Interrupt Level Selected None VMEbus Interrupter disabled Level 1 Level 2 Level...

Страница 59: ...out out out out In In In In out out out out In In In In out out out out In In In In out out out out In In In In out out out out In In JAI1 In In out out In In out out In In out out In In out out In In...

Страница 60: ...800H out In out out out o u t BCOOH out o u t In In In In COOOH out out In In In o u t C4OOH out out In In out In C800H out out In In out o u t CCOOH out out In out In In DOOOH out out In out In o u t...

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