XMOS VocalFusion XVF3510, Руководство пользователя

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XM-014232-PC 43
The SPI master peripheral supports the following fixed specifications:
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Single chip select line
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1Mbps fixed clock speed
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Supports either reads or writes. Duplex read/writes are not supported.
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Most significant bit transferred first
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Mode 0 transfer (CPOL = 0, CPHA = 0)
NOTE: The chip select is asserted a minimum of before 20ns the start of the transfer and de-asserted
a minimum of 20ns after the transfer ends.
The SPI Master is controlled using the following commands.
Table 4-7 SPI peripheral interface commands
COMMAND TYPE DIR ARGS DESCRIPTION
GET_SPI uint8 READ 56 Gets the contents of the SPI read buffer.
GET_SPI_READ_HEADER uint8 READ 2 Get the address and count of next SPI read.
SET_SPI_PUSH uint8 WRITE 56 Push SPI command data onto the execution queue.
SET_SPI_PUSH_AND_EXEC uint8 WRITE 56
Push SPI command data and execute the command from the
stack. Data will then be sent to SPI device.
SET_SPI_READ_HEADER uint8 WRITE 2 Set address and count of next SPI read.
Reads of up to 56 Bytes at a time may be performed but writes of 128 Bytes at a time can be made by
pushing multiple commands into a command stack and executing them in one go. The transaction is
performed within a single chip select assertion.
Figure 4-7 SPI peripheral, read sequence
Figure 4-8 SPI peripheral, write sequence