Xilinx Virtex-II Pro, Руководство пользователя

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Virtex-II Pro Prototype Platform User Guide www.xilinx.com 19
UG027 / PN 0402044 (v1.6) October 25, 2002 1-800-255-7778
Detailed Description
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10. Differential Clock Inputs
In addition to the oscillator sockets, there are eight 50
Ω
SMA connectors that allow
connection to an external function generator. These connect to the DUT clock pads as
shown in
Table 1-5 . They can also be used as differential pairs with 100
Ω
termination
resistors. The differential clock pairings are as shown.
11. DUT Socket
The DUT socket contains the user FPGA, referred to as the Device Under Test.
The device must be oriented using the P1 indicator on the board. Failure to insert the
device to the proper orientation can damage the device. To avoid pin damage, always use
the vacuum tool provided when inserting or removing the Virtex-II Pro device. When
Table 1-4: OSC Clock Pin Connections
FG456 FF672 FF1152
Label
Clock
Name Pin
Number
Clock
Name Pin
Number
Clock
Name Pin
Number
OSC Socket Top1 GCLK0S F12 GCLK0S E14 GCLK0S E18
OSC Socket
Bottom 2 GCLK1P E12 GCLK1P D14 GCLK1P D18
OSC Socket
Bottom 1 GCLK2P V12 GCLK2P AB14 GCLK2P AJ17
OSC Socket Top 2 GCLK3S U12 GCLK3S AC13 GCLK3S AH18
Table 1-5: SMA Clock Pin Connections
FG456 FF672 FF1152
Label
Clock
Name Pin
Number
Clock
Name Pin
Number
Clock
Name Pin
Number
N GCLK1S W12 GCLK4P AD13 GCLK4P AK17
P GCLK0P Y12 GCLK5S AE13 GCLK5S AL17
N GCLK3P C12 GCLK6P B13 GCLK6P H17
P GCLK2S D12 GCLK7S C13 GCLK7S J17
N GCLK7S Y11 GCLK7P AE14 GCLK7P AL18
P GCLK6P W11 GCLK6S AD14 GCLK6S AK18
N GCLK5P D11 GCLK5P C14 GCLK5P J18
P GCLK4S C11 GCLK4S B14 GCLK4S H18
Notes:
1. Use these differential clock pairs for the Rocket I/O transceivers. They have been optimized for the
transceivers.
2. These global clocks are not available through the breakout area test points.