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Virtex-II Pro Prototype Platform User Guide

www.xilinx.com

UG027 / PN 0402044 (v1.6) October 25, 2002

1-800-255-7778

Detailed Description

The voltage regulators deliver fixed voltages. Maximum current range for each supply is
2A.

Table 1-1

shows the maximum voltage for each power supply jack.

Note:

To power the V

CCAUX

pins you must jumper the pins labeled VAUX enable located next to

the VCCAUX jack on the board. This action will connect the V

CCAUX

pins on the DUT to V

CCO

Off Position

In the off position, the power switch disables all modes of powering the DUT.

Power Enable Jumpers

For each power supply there are headers marked

Supply

on one side and

Jack

on the other

side. Appropriate placements of jumpers on these headers enables delivery of all power
from either the onboard regulators or the four power supply jacks marked

VCORE

VCCO

VCCAUX

, and

MGT_VCC

2. Power Supply Jacks

One method of delivering power to the DUT is by way of the power supply jacks. (Consult
the Xilinx data book,

http://www.xilinx.com/partinfo/databook.htm

, for the maximum

voltage rating for each device you are using.) The power supply jacks are:

•

VCORE

♦

Supplies voltage to the core of the DUT

•

VCCO

♦

Supplies I/O voltages to the DUT

♦

Each bank can be powered from one of two sources (V

CCO

, V

CCINT

) by

appropriate placement of jumpers on the header

•

VCCAUX

♦

Supplies voltage to the V

AUX

header and the V

AUX

DUT pins

•

MGT_VCC

♦

Supplies power to the Rocket I/O transceivers on the DUT (AV

AUX, VTT

VTR

)

Table 1-1:

Voltage Ranges

Label

Max Voltage

VCORE

1.5V

VCCO

2.5V

VCCAUX

2.5V

MGT_VCC

2.5V

Содержание Virtex-II Pro

Страница 1: ...R Virtex II Pro Prototype Platform User Guide UG027 PN 0402044 v1 6 October 25 2002...

Страница 2: ...Virtex II Pro Prototype Platform User Guide www xilinx com UG027 PN 0402044 v1 6 October 25 2002 1 800 255 7778...

Страница 3: ...rcuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or informati...

Страница 4: ...table shows the revision history for this document Date Version Revision 03 04 02 1 0 Preliminary Xilinx release 05 29 02 1 1 Initial Xilinx release 06 04 02 1 2 Modifications to Figure 1 1 06 11 02 1...

Страница 5: ...15 3 Configuration Ports 16 4 JTAG Termination Jumper 16 5a Upstream System ACE Connector 17 5b Downstream System ACE Connector 18 6 Prototyping Area 18 7 VCCO Enable Supply Jumpers 18 8 VBATT 18 9 O...

Страница 6: ...Virtex II Pro Prototype Platform User Guide www xilinx com UG027 PN 0402044 v1 6 October 25 2002 1 800 255 7778...

Страница 7: ...xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL Tutorials Tuto...

Страница 8: ...ple Courier font Messages prompts and program files that the system displays speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name Helvetica bold...

Страница 9: ...has been omitted allow block block_name loc1 loc2 locn Convention Meaning or Use Example Convention Meaning or Use Example Blue text Cross reference link to a location in the current file or in anothe...

Страница 10: ...10 www xilinx com Virtex II Pro Prototype Platform User Guide 1 800 255 7778 UG027 PN 0402044 v1 6 October 25 2002 Preface About This Manual R...

Страница 11: ...the board Bitstream synthesized using Xilinx ISE 4 2i tools Full schematics of the board in both PDF format and ViewDraw schematic format PC board layout in Pads PCB format Gerber files in pho and pdf...

Страница 12: ...onfiguration Interface connectors Onboard battery holder Two low voltage 14 pin DIP crystal oscillators The kit contains headers that can be soldered to the breakout area if desired These headers are...

Страница 13: ...em ACE Upstream LEDs UG027_01_102502 Done LED Init LED VBATT Program User Reset SDRAM 10 ns 64 Mb 8 MB To Test Points on All Pins SPROM 18v04 x 2 System ACE Downstream LVTTL 2x 2x Diff Pair Clocks SMA...

Страница 14: ...e board has an onboard power supply and an on off power switch When lit a green LED indicates power from the power brick connector or the 5V jack On Position In the on position the power switch enable...

Страница 15: ...Appropriate placements of jumpers on these headers enables delivery of all power from either the onboard regulators or the four power supply jacks marked VCORE VCCO VCCAUX and MGT_VCC 2 Power Supply J...

Страница 16: ...TDO pin of the upstream System ACE connector for the final board in a chain TCK and TMS are parallel feedthrough connections from the upstream System ACE connector to the downstream System ACE connect...

Страница 17: ...to generate very large JTAG streams for configuring multiple Virtex II Pro Prototype Platforms using the Downstream System ACE connector Table 1 3 JTAG Mode Configuration Port Header Parallel IV Cabl...

Страница 18: ...one of the two onboard supplies VCCINT or the VCCO supply These jumpers must be installed for the Virtex II Pro device to function normally 8 VBATT An onboard battery holder is connected to the VBATT...

Страница 19: ...ng the Virtex II Pro device When Table 1 4 OSC Clock Pin Connections FG456 FF672 FF1152 Label Clock Name Pin Number Clock Name Pin Number Clock Name Pin Number OSC Socket Top1 GCLK0S F12 GCLK0S E14 GC...

Страница 20: ...tion mode switch During configuration the LEDs are in a high impedance condition After configuration the LEDs are available to the user and reflect the status of pins D0 D7 corresponding to LED 0 LED...

Страница 21: ...ights when DONE is high or if power is applied to the board without a part in the socket 17 INIT LED The INIT LED lights during initialization User Programmable Pins 18 Rocket I O Transceiver Pins Tab...

Страница 22: ...ng from the SDRAM to the available DUT package types Table 1 10 System Clock for SDRAM and DUT SDRAM Pin FG456 FF672 FF1152 CLK E12 D14 D18 Table 1 11 SDRAM to FPGA Pin Mapping SDRAM Pin FG456 FF672 F...

Страница 23: ...64323LF S D G S75 For information on its operation see http www samsungelectronics com semiconductors DRAM Mobile_SDRAM 64M_bit K4S64323 LF ds_k4s64323lf s d g_s pdf DQ27 E1 C2 K4 DQ28 E3 C1 L7 DQ29 D...

Страница 24: ...tions for the available DUT package types For details on CPU debug pins refer to Appendix A RISCWatch and RISCTrace Interfaces Figure 1 6 CPU Debug Connector 16 Pin Male Table 1 12 CPU Debug Pins Pin...

Страница 25: ...age types For details on CPU debug pins refer to Appendix A RISCWatch and RISCTrace Interfaces Figure 1 7 CPU Trace Connector 20 Pin Male Table 1 13 RISC Trace Pins Pin FG456 FF672 FF1152 TS5 V22 AB24...

Страница 26: ...232 Port Pins Pin FG456 FF672 FF1152 T1IN Y2 AC1 AF10 T2IN T4 AC2 AH10 R1OUT U4 AD2 AE11 R2OUT V4 AD1 AG10 Figure 1 8 38 Pin Mictor Connector UG027_08_030402 Reserved for EXTTRIG Reserved for DBGACK T...

Страница 27: ...Mictor connector are included in the signal mapping tables RISCWatch Interface The RISCWatch tool communicates with the PPC405x3 using the JTAG and debug interfaces It requires a 16 pin male 2x8 heade...

Страница 28: ...gnal to reduce chip power consumption The pull up resistor is not required 2 The POWER signal is provided by the board and indicates whether the processor is operating This signal does not supply powe...

Страница 29: ...d in Table A 4 At the board level the connector should be placed as close as possible to the processor chip to ensure signal integrity An index at pin one and a key notch on the same side of the conne...

Страница 30: ...nal Mapping PPC405x3 RISCTrace Trace Connector Pin Mictor Connector Pin Signal I O Signal I O C405TRCCYCLE Output TrcClk Input 3 6 C405TRCODDEXECUTIONSTATUS 0 Output TS1O Input 12 24 C405TRCODDEXECUTI...

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