Spartan-6 FPGA Power Management
www.xilinx.com
21
UG394 (v1.1) September 4, 2012
SUSPEND Input Glitch Filter
SUSPEND Input Glitch Filter
The SUSPEND pin has a programmable glitch filter to guard against short pulses, which
could cause the FPGA to spuriously enter suspend mode. Turning off the filter allows the
FPGA to enter or exit suspend mode more quickly, but the application must guard against
spurious pulses. The difference in delay is the t
SUSPENDFILTER
value in
DS162
,
Spartan-6
FPGA Data Sheet: DC and Switching Characteristics
. See
Enable the Suspend Feature and
Glitch Filtering, page 14
.
SUSPEND_SYNC Primitive
The SUSPEND_SYNC primitive is the application interface to a suspend request. If this
primitive is not present in the design, the FPGA begins the suspend sequence solely on the
state of the SUSPEND pin.
When the SUSPEND_SYNC primitive is in the design, after the SUSPEND pin is asserted
High and the filter delay (when the glitch filter is enabled), the SUSPEND_SYNC primitive
drives the SREQ port High on the next rising clock edge on the CLK port. This indicates
that a request has been received to enter suspend mode. The FPGA does not enter suspend
mode until the SACK port is driven High on a rising edge of CLK.
This primitive provides an ideal interface for the application to complete any functions
prior to entering suspend mode. Any I/O interface ports can be closed, buffers flushed,
and clocks disabled to ensure the application is in a ready state prior to being suspended.
For more details, see
Design Maintained during Suspend Mode, page 16
.
AWAKE Pin
The AWAKE pin (optionally) provides status on the suspend power-savings mode.
General Behavior (Suspend Feature Disabled)
Unless the suspend feature is enabled, the AWAKE pin is a general-purpose user-I/O pin.
AWAKE Pin Behavior when Suspend Feature is Enabled
If the suspend feature is enabled, then the AWAKE pin indicates the present state of the
FPGA, as summarized in
Table 1-6
. The AWAKE pin cannot be used by the FPGA
application as a general-purpose I/O pin.
The AWAKE pin can further be configured as an open-drain output (the default) or a
full-swing output driver, as shown in
Figure 1-5
. This behavior is controlled by a bitstream
generator (BitGen) option:
bitgen -g drive_awake:no
Table 1-6:
AWAKE Pin Status
AWAKE Pin
Indication
0
The FPGA is presently in the low-power suspend mode.
1
The FPGA is active.
