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Spartan-6 FPGA Power Management

UG394 (v1.1) September 4, 2012

Chapter 1:

Power Management With Suspend Mode

Suspend Features

The significant features and benefits of the suspend mode:

•

Quickly and easily puts the FPGA into a static condition, eliminating most active
current.

•

Reduces quiescent current by 40% or more.

•

Retains FPGA configuration data and the state of the FPGA application during
suspend mode.

•

Fast, programmable FPGA wake-up time from suspend mode.

•

Individual control on each user-I/O pin to define pin behavior while in suspend
mode.

•

Activated externally by the system using a single dedicated control pin (SUSPEND).

•

Indicates the present suspend mode status using the AWAKE pin.

•

Awakens an FPGA in suspend mode using any of eight SUSPEND control pins (SCP).

•

SUSPEND_SYNC primitive to acknowledge a ready state prior to entering suspend
mode.

Design Steps

To use the suspend feature:

•

Enable the Suspend Feature and Glitch Filtering, page 14

•

Define the Multi-Pin Wake-Up Feature and Pins, page 15

•

Define the I/O Behavior During Suspend Mode, page 15

•

Implement steps to maintain application data during suspend mode
(SUSPEND_SYNC) (see

Design Requirements to Maintain Application Data, page 17

)

•

Define the

Suspend Mode Wake-Up Timing Controls, page 17

•

Define the

AWAKE Pin Behavior when Suspend Feature is Enabled, page 21

Entering Suspend Mode

Figure 1-1

is a block diagram of the FPGA entering suspend mode.

Figure 1-2, page 10

shows example waveforms.

Содержание Spartan-6 FPGA Series

Страница 1: ...Spartan 6 FPGA Power Management User Guide UG394 v1 1 September 4 2012...

Страница 2: ...and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Copyright 2010 2012 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Zynq...

Страница 3: ...eature and Pins 15 Define the I O Behavior During Suspend Mode 15 Single Ended I O Standards 15 Differential I O Standards 15 SUSPEND Attribute 16 UCF Example 16 Design Maintained during Suspend Mode...

Страница 4: ...3 Lower Power Spartan 6 LX Devices Introduction 29 Designing Using the Lower Power Spartan 6 LX Devices 29 Lower Power Spartan 6 LX Device Specifications 30 Chapter 4 Power On and Power Down Behavior...

Страница 5: ...n These documents are available for download at http www xilinx com support documentation spartan 6 htm Spartan 6 Family Overview This overview outlines the features and product selection of the Spart...

Страница 6: ...making design decisions at the PCB and interface level These documents provide additional background WP298 Power Consumption at 40 nm and 45 nm White Paper At 40 and 45 nm process nodes power has beco...

Страница 7: ...PGAs is a superset of the suspend feature in the Extended Spartan 3A FPGAs Two new enhancements include multi pin wake up and suspend synchronization Multi Pin Wake up The multi pin wake up feature al...

Страница 8: ...SUSPEND Indicates the present suspend mode status using the AWAKE pin Awakens an FPGA in suspend mode using any of eight SUSPEND control pins SCP SUSPEND_SYNC primitive to acknowledge a ready state p...

Страница 9: ...mode When these functions are complete drive the SACK port High After the FPGA enters suspend mode all nonessential FPGA functions are shut down to minimize power dissipation The FPGA retains all conf...

Страница 10: ...the SUSPEND_SYNC primitive is asserted Data values are captured for I O pins with a SUSPEND attribute set to DRIVE_LAST_VALUE however this value is not presented until Step 4 2 In response to the SUS...

Страница 11: ...High before the FPGA continues to awaken All subsequent timing is measured from when the AWAKE output transitions High If multiple FPGAs are waking up and need to be synchronized set drive_awake no in...

Страница 12: ...ll inputs and interconnects after a delay of tSUSPEND_ENABLE If using multi pin wake up mode SUSPEND must first transition Low then when any of the user enabled SCP pins for multi pin wake up mode tra...

Страница 13: ...Latches Block RAM Writable Clocked Primitives FPGA Application Logic FPGA Inputs FPGA Outputs Re enable FPGA Inputs Set Reset Flip Flops SUSPEND AWAKE Enable Unlock Clocked Primitives Activate Outputs...

Страница 14: ...ints File Enable Suspend mode is enabled and the SUSPEND input glitch filter option is defined using a CONFIG statement in a UCF Table 1 1 shows the available options This is the recommended method fo...

Страница 15: ...f the suspend mode behaviors shown in Table 1 2 The default behavior is for a high impedance pin during suspend mode although other options are available Differential I O Standards The output drivers...

Страница 16: ...pin and a differential pair are shown in the following example NET TX 0 IOSTANDARD LVCMOS_33 SUSPEND DRIVE_LAST_VALUE NET TX_P 0 IOSTANDARD LVDS_33 SUSPEND 3STATE_PULLUP NET TX_N 0 IOSTANDARD LVDS_33...

Страница 17: ...USPEND_SYNC feature After the suspend request is driven out of the SUSPEND_SYNC primitive disable the clocks and or clock enables on the logic that must retain its current state After the disable is c...

Страница 18: ...nternal Oscillator Cclk Jtag UserClk CCLK TCK STARTUP_SPARTAN6 StartupClk CLK CCLK input only available for applications that configure in Slave mode Persist Yes required User Clock from FPGA Intercon...

Страница 19: ...e write protect lock is released on all clocked primitives The timing is controlled by sw_clk the Wake Up Timing Clock Source page 17 The default sw_gwe_cycle setting is five cycles but the suspend wa...

Страница 20: ...er is supplied by the VCCAUX power rail The SUSPEND pin has no pull up resistors during configuration and the HSWAPEN control has no effect on the SUSPEND pin Table 1 4 JTAG Operations Allowed during...

Страница 21: ...est has been received to enter suspend mode The FPGA does not enter suspend mode until the SACK port is driven High on a rising edge of CLK This primitive provides an ideal interface for the applicati...

Страница 22: ...PGAs and the system by using one SUSPEND signal to control multiple devices The AWAKE pin can also synchronize multiple devices To start the wake up process at the same time the AWAKE pins of multiple...

Страница 23: ...AKE pin transitions High and before the sw_gwe_cycle and sw_gts_cycle settings are active sw_clk StartupClk Default Uses the clock defined by the StartupClk bitstream generator setting to control the...

Страница 24: ...mode but this also affects the voltage levels for any output pin with a SUSPEND attribute set to DRIVE_LAST_VALUE The FPGA s power on reset POR circuit continues to monitor the VCCINT and VCCAUX supp...

Страница 25: ...s block RAM and DSP blocks Input to the power on reset POR circuit Powers input signals for most standards at 1 2V 1 5V and 1 8V All 1 2V 1 0V 1L in lower power Spartan 6 LX devices VCCAUX Auxiliary s...

Страница 26: ...Switching Characteristics VCCO_4 Supplies the output buffers in I O bank 4 the bank along the top of the left edge of the FPGA in 6 bank devices LX75 T LX100 T and the LX150 T in FG G 676 and FG G 900...

Страница 27: ...ment There are some slight changes to resistor values depending on whether VCCAUX is set to 2 5V or 3 3V The I O pull down resistor values are lower for a VCCAUX of 3 3V The differential termination r...

Страница 28: ...feature size reduction and reduced power consumption have reduced core voltages down to the 1 0V range This change in voltage and signal frequency content requires the use of advanced design practices...

Страница 29: ...primitives that support the Spartan 6 LX family also support the lower power Spartan 6 LX devices The lower power Spartan 6 LX devices can be selected using the ISE Design Suite in the Project Naviga...

Страница 30: ...namic current and power See Chapter 5 Power Estimation Because of the reduction in maximum VCCINT the maximum time for ramping up is shorter See the VCCINTR ramp time specification in DS162 Spartan 6...

Страница 31: ...ompliance of the I O allowing the FPGA to be moved in or out of a powered system without damage Power On Reset Spartan 6 FPGAs have a built in power on reset POR circuit that monitors the three power...

Страница 32: ...e Precautions in UG380 Spartan 6 FPGA Configuration User Guide Ramp Rate The power supplies should ramp monotonically within the power supply ramp time range specified in DS162 Spartan 6 FPGA Data She...

Страница 33: ...ure the FPGA GTP Transceiver Power Up and Power Down All GTP_DUAL tiles are reset automatically after configuration The supplies for the calibration resistor and calibration resistor reference must be...

Страница 34: ...ration source The FPGA must reconfigure before the application restarts No state information is preserved If the application must retain the FPGA configuration bitstream then use the suspend mode Ente...

Страница 35: ...ut any unwanted transitions Figure 4 3 shows the waveforms for entering and exiting Hibernate The steps for entering Hibernate are as follows 1 Pull the PROGRAM_B pin Low to force all user I O pins in...

Страница 36: ...ion process 4 When configuration is complete the FPGA enters the Start up phase asserts DONE and enables the I Os according to how the BitGen options are set 5 The FPGA is now ready for user operation...

Страница 37: ...upply and thermal management components For comparison and analysis the XPE spreadsheet for the Spartan 6 family also includes the Extended Spartan 3A family XPE considers the resource usage toggle ra...

Страница 38: ...partan 3A FPGAs the average static power in Spartan 6 devices is lower Quiescent current levels are specified in DS162 Spartan 6 FPGA Data Sheet DC and Switching Characteristics The lower power Sparta...

Страница 39: ...linx software automatically disables clock nets where possible for unused areas of CLBs If possible minimize the number of DCMs or PLLs required in the design A single PLL can be shared with both halv...

Страница 40: ...40 www xilinx com Spartan 6 FPGA Power Management UG394 v1 1 September 4 2012 Chapter 5 Power Estimation...

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