Spartan-6 FPGA Power Management
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33
UG394 (v1.1) September 4, 2012
Configuration Data Retention and Brown Out
Configuration Data Retention and Brown Out
The FPGA's configuration data is stored in robust CMOS configuration latches. The data in
these latches is retained even when the voltages drop to the minimum levels necessary to
preserve RAM contents, as specified in
DS162
,
Spartan-6 FPGA Data Sheet: DC and
Switching Characteristics
(V
DRINT
and V
DRAUX
).
After configuration, if the V
CCAUX
or V
CCINT
supply drops below its minimum data
retention voltage, the integrity of the CMOS configuration latches is no longer guaranteed,
and the current device configuration must be cleared using one of the following methods:
•
Force the V
CCAUX
or V
CCINT
supply voltage to GND, then raise the voltages back to
the recommended operating range (as shown in
DS162
,
Spartan-6 FPGA Data Sheet:
DC and Switching Characteristics
)
•
Assert PROGRAM_B Low, then raise it back High
The POR circuit does not monitor the V
CCO_2
supply after configuration. Consequently,
dropping the V
CCO_2
voltage does not reset the device by triggering a POR event. The
PROGRAM_B input bypasses the POR circuit (see
Figure 4-1, page 31
) and therefore can
be used as an independent means to initialize the FPGA.
After the INIT_B signal goes High to indicate successful clearing of the FPGA, reconfigure
the FPGA.
GTP Transceiver Power-Up and Power-Down
All GTP_DUAL tiles are reset automatically after configuration. The supplies for the
calibration resistor and calibration resistor reference must be powered up before
configuration to ensure correct calibration of the termination impedance of all transceivers.
The reference clock and the power to the GTP_DUAL tile must be available before
configuring the FPGA. If the reference clock or GTP_DUAL tile is powered up after
configuration, apply GTPRESET to allow the PMA PLL to lock.
The GTP transceiver supports a range of power-down modes. These modes support both
generic power management capabilities as well as those defined in the PCI Express and
SATA standards.
Each channel in each direction can be powered down separately using TXPOWERDOWN
and RXPOWERDOWN. Each PLLPOWERDOWN port directly affects the associated PLL
that is selected by the PLL_SOURCE attribute.
For more details on the GTP Transceivers, see
UG386
,
Spartan-6 FPGA GTP Transceivers
User Guide
, Managing Used and Unused GTP Transceivers, Board Design Guidelines.
Hibernate Power Down
Hibernate is effectively powering down the FPGA (
Figure 4-2
). Due to the hot swap
compliance of the Spartan-6 family, this is allowed even if external devices are still
providing active signals to the FPGA. The FPGA loses its configuration data and must be
re-programmed after power-on. Hibernate provides the maximum possible power savings
for applications that can be turned off for long periods of time and that can afford to lose
the present design state.
