Spartan-6 FPGA Power Management
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19
UG394 (v1.1) September 4, 2012
Dedicated Configuration Pins Unaffected During Suspend Mode
Switch Outputs from Suspend to Normal Behavior
The suspend/wake
sw_gts_cycle
bitstream option controls when I/O pins are released
from their SUSPEND attribute settings and returned to normal operation. The timing is
controlled by the
Wake-Up Timing Clock Source, page 17
. The default
sw_gts_cycle
setting
is four cycles, but this control can be set for any value between one and 1,024 clock cycles.
The suspend/wake control becomes active after the AWAKE pin transitions High. After
the specified number of clock cycles, all output, open-drain output, and bidirectional I/O
pins transition from their suspend behavior, either the default 3STATE or individually
specified using the SUSPEND attribute, back to the normal behavior specified in the
original FPGA application.
The outputs should be released before releasing the write-protect lock on all clocked
primitives.
Release Write Protect on Clocked Primitives
The suspend/wake
sw_gwe_cycle
bitstream option controls when the write-protect lock is
released on all clocked primitives.
The timing is controlled by
sw_clk
the
Wake-Up Timing Clock Source, page 17
. The default
sw_gwe_cycle
setting is five cycles, but the suspend/wake control can be set for any value
between one and 1,024 clock cycles.
This suspend/wake control becomes active after the AWAKE pin transitions High. After
the specified number of clock cycles, the write-protect lock is released from all writable,
clocked primitives such as flip-flops, block RAM, etc.
When the
en_sw_gsr:yes
option is set, the clocked primitives are already globally set or
reset to the value specified in the original FPGA design before the write-protect lock is
released. The option
en_sw_gsr:no
signifies that the state of the FPGA after entering
suspend mode is preserved.
The outputs should be released before releasing the write-protect lock on all clocked
primitives.
Dedicated Configuration Pins Unaffected During Suspend Mode
The following dedicated configuration pins are unaffected when the FPGA is in suspend
mode:
•
JTAG pins: TDI, TMS, TCK, and TDO
•
DONE pin
•
PROGRAM_B pin
JTAG Operations Allowed During Suspend Mode
Table 1-4
shows the JTAG operations permitted when the FPGA is in suspend mode.
Executing these JTAG operations increases the FPGA's power consumption while in
suspend mode.
