Xilinx ML623, Руководство пользователя

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8 www.xilinx.com ML623 Board User Guide
UG724 (v1.1) September 15, 2010
Chapter 1: ML623 Board Features and Operation
Detailed Description
Figure 1-2 shows the ML623 board described in this user guide. Each numbered feature
that is referenced in Figure 1-2 is described in the sections that follow.
Note:
The image in Figure 1-2 is for reference only and might not reflect the current revision of the
board.
X-Ref Target - Figure 1-1
Figure 1-1: ML623 Board Block Diagram
UG724_c1_01_043010
V
irtex-6 FPGA
XC6 V LX240T-2FFG1156C
12 V Po w er In
FMC Interface
FMC1 FMC2 FMC3
(A N SI/ V ITA 57.1-2008 v 1.1)
System ACE
Controller
System Monitor
Interface
I2C B u s Management
GTX Transcei
v
er
Po w er Mod u le
FPGA Po w er So u rce
On- b oard Reg u lation:
V
CCI
N
T 1.0
V
at 20 Amps
V CCO 2.5 V at 20 Amps
V CCAUX 2.5 V at 20 Amps
A u xiliary Po w er
On- b oard Reg u lation:
5.0 V at 8 Amps
3.3
V
at 20 Amps
2.5 V at 20 Amps
GTX QUAD_114
Transcei v er and
Transcei v er Clock SMA
User GPIO
P
u
sh B
u
ttons,
DIP S w itches,
and LEDs
200 MHz L V DS Clock,
Differential User SMA Clocks,
Singe-Ended User SMA Clocks
S u perClock-2 Mod u le
USB to UART
Bridge
GTX QUAD_113
Transcei v er and
Transcei v er Clock SMA
GTX QUAD_112
Transcei v er and
Transcei v er Clock SMA
GTX QUAD_115
Transcei v er and
Transcei v er Clock SMA
GTX QUAD_116
Transcei v er and
Transcei v er Clock SMA