Xilinx ML623, Руководство пользователя

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ML623 Board User Guide www.xilinx.com 17
UG724 (v1.1) September 15, 2010
Detailed Description
Table 1-4 indicates the FPGA pin name associated with each jumper.
200 MHz 2.5V LVDS Oscillator
[ Figure 1-2 , callout 10 ]
The ML623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
Table 1-5 lists the FPGA pin connections to the LVDS oscillator.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1–3 and 2–4 (LVDS).
Single-Ended SMA Global Clock Inputs
[ Figure 1-2 , callout 11 ]
The ML623 board provides two single-ended clock input SMA connectors that can be used
for connecting to an external function generator. The FPGA clock pins are connected to the
SMA connectors as shown in
Table 1-6 .
To use these clock inputs, remove jumpers across AFX SEL headers J186 and J187.
X-Ref Target - Figure 1-6
Figure 1-6: JTAG Isolation Jumpers
Table 1-4: JTAG Isolation Jumpers
Reference Designator FPGA Pin Name
J22 TMS
J23 TDI
J195 TDO
J196 TCK
UG724_c1_06_040610
J196
J195
J23
J22
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
U25
TCK
TDO
TDI
TMS
FPGA
U1
Table 1-5: LVDS Oscillator Global Clock Connections
FPGA Pin Net Name U7 Pin
J9 IO_LVDS_CLK_P 4
H9 IO_LVDS_CLK_N 5