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ML623 Board User Guide

www.xilinx.com

UG724 (v1.1) September 15, 2010

Detailed Description

User Test I/O

[

Figure 1-2

, callout

]

A standard 2 x 6, 100-mil pitch header (J197) brings out 6 FPGA I/O for test purposes.

Table 1-12

lists these pins.

GTX Transceiver Pins

[

Figure 1-2

, callout

]

All FPGA GTX transceiver pins are connected to differential SMA connector pairs. The
GTX transceivers are grouped into five sets of four (referred to as

Quads)

which share two

differential reference clock pin pairs (

Figure 1-7

). The transceiver pins and their

corresponding SMA connector are shown in

Table 1-13

Table 1-12:

User Test I/O

FPGA Pin

Net Name

J197 Pin

U30

IO_L8N_SRCC_14_U30

U31

IO_L8P_SRCC_14_U31

D32

IO_L15N_16_D32

D31

IO_L15P_16_D31

K27

IO_L9N_MRCC_16_K27

K26

IO_L9P_MRCC_16_K26

Содержание ML623

Страница 1: ...ss mainly focus on the distribution of electronic components Line cards we deal with include Microchip ALPS ROHM Xilinx Pulse ON Everlight and Freescale Main products comprise IC Modules Potentiometer...

Страница 2: ...ML623 Virtex 6 FPGA GTX Transceiver Characterization Board User Guide UG724 v1 1 September 15 2010...

Страница 3: ...you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOC...

Страница 4: ...figuration 14 PROG Push Button 15 DONE LED 15 INIT LED 15 System ACE Controller 16 System ACE Controller Reset 16 Configuration Address DIP Switches 16 JTAG Isolation Jumpers 16 200 MHz 2 5V LVDS Osci...

Страница 5: ...w xilinx com ML623 Board User Guide UG724 v1 1 September 15 2010 Appendix A Default Jumper Positions Appendix B VITA 57 1 FMC HPC Connector Pinout Appendix C ML623 Master UCF Listing Appendix D Refere...

Страница 6: ...itions lists the jumpers that must be installed on the board for proper operation Appendix B VITA 57 1 FMC HPC Connector Pinout provides a pinout reference for the FPGA mezzanine card FMC connector Ap...

Страница 7: ...File Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Command Line Tools User Guide...

Страница 8: ...able III IV cables System ACE controller Power module supporting all Virtex 6 FPGA GTX transceiver power requirements A fixed 200 MHz 2 5V LVDS oscillator wired to global clock inputs Two single ended...

Страница 9: ...e FMC1 FMC2 FMC3 ANSI VITA 57 1 2008 v1 1 System ACE Controller System Monitor Interface I2C Bus Management GTX Transceiver Power Module FPGA Power Source On board Regulation VCCINT 1 0V at 20 Amps VC...

Страница 10: ...J31 J33 J102 J104 J105 13 SuperClock 2 module 1e Regulation Inhibit J14 J19 14 User LEDs active High DS10 DS17 1f External power supply jacks 15 User DIP switches active High SW7 1g TI PMBus connector...

Страница 11: ...12V AC adapter included with the board J122 is a 6 pin 2 x 3 right angle Mini Fit type connector Power can also be provided through Connector J141 which accepts an ATX hard disk 4 pin power plug Jack...

Страница 12: ...h voltage See Using External Power Sources X Ref Target Figure 1 3 Figure 1 3 ML623 Board Power Supply Block Diagram External Supply Jacks VCCINT VCCAUX VCCO VCC2V5 UG724_c1_03_040810 VCC3V3 VCC5 Powe...

Страница 13: ...ing a jumper across pins 2 3 of header J19 Default Jumper Positions A list of shunts and shorting plugs and their required positions for normal board operation is provided in Appendix A Default Jumper...

Страница 14: ...of the three modules can be plugged into connectors J34 and J179 in the outlined and labeled power module location shown in Figure 1 4 Table 1 2 describes the nominal voltage values for the MGTAVCC a...

Страница 15: ...nly using one of the following options Platform Cable USB Parallel Cable IV Parallel Cable III System ACE controller Detailed information on the System ACE controller is available in DS080 System ACE...

Страница 16: ...e state of the DONE pin of the FPGA When the DONE pin is High DS6 lights indicating the FPGA is successfully configured INIT LED Figure 1 2 callout 5 The INIT LED DS20 lights during FPGA initializatio...

Страница 17: ...h SW3 selects one of the eight configuration bitstream addresses in the CompactFlash memory card The switch settings for selecting each address are shown in Table 1 3 JTAG Isolation Jumpers Figure 1 2...

Страница 18: ...Clock Inputs Figure 1 2 callout 11 The ML623 board provides two single ended clock input SMA connectors that can be used for connecting to an external function generator The FPGA clock pins are conne...

Страница 19: ...The clock module maps to FPGA I O by way of 24 control pins 3 LVDS pairs 1 regional clock pair and 1 reset pin Table 1 8 shows the FPGA I O mapping for the SuperClock 2 module interface The ML623 boa...

Страница 20: ...5 K21 CM_CTRL_3 67 A19 CM_CTRL_4 69 A18 CM_CTRL_5 71 J22 CM_CTRL_6 73 H22 CM_CTRL_7 75 D19 CM_CTRL_8 77 E19 CM_CTRL_9 79 E21 CM_CTRL_10 81 D21 CM_CTRL_11 83 H20 CM_CTRL_12 85 H19 CM_CTRL_13 87 A20 CM_...

Страница 21: ...ns Active High Figure 1 2 callout 16 SW5 and SW6 are active High user push buttons that are connected to user I O pins on the FPGA as shown in Table 1 11 These switches can be used for any purpose det...

Страница 22: ...TX transceiver pins are connected to differential SMA connector pairs The GTX transceivers are grouped into five sets of four referred to as Quads which share two differential reference clock pin pair...

Страница 23: ...3 QUAD_114 QUAD_115 QUAD_112 QUAD_116 112 Clocks 115 Clocks 113 Clocks 114 Clocks 116 Clocks 114 Clocks Table 1 13 GTX Transceiver Pins FPGA Pin Net Name SMA Connector Trace Length Mils AP5 112_RX0_P...

Страница 24: ...113_TX1_P J63 6 520 AF2 113_TX1_N J62 6 528 AE3 113_RX2_P J79 8 300 AE4 113_RX2_N J78 8 307 AD1 113_TX2_P J77 7 553 AD2 113_TX2_N J76 7 558 AC3 113_RX3_P J80 7 166 AC4 113_RX3_N J75 7 175 AB1 113_TX3...

Страница 25: ...0 K2 115_TX1_N J126 7 650 K5 115_RX2_P J120 6 957 K6 115_RX2_N J121 6 964 H1 115_TX2_P J118 7 669 H2 115_TX2_N J117 7 665 J3 115_RX3_P J116 7 397 J4 115_RX3_N J114 7 387 F1 115_TX3_P J111 7 626 F2 115...

Страница 26: ...3 116_TX3_P J140 10 663 A4 116_TX3_N J139 10 659 Table 1 13 GTX Transceiver Pins Cont d FPGA Pin Net Name SMA Connector Trace Length Mils Table 1 14 GTX Transceiver Clock Inputs to the FPGA FPGA Pin N...

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