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Xilinx M401 Скачать руководство пользователя страница 30

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ML401/ML402/ML403 Evaluation Platform

UG080 (v2.5) May 24, 2006

Detailed Description

R

29. DONE LED

The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted
when the FPGA is successfully configured.

30. Program Switch

This switch grounds the FPGA's Prog pin when pressed. This action clears the FPGA.

31. Configuration Address and Mode DIP Switches

This 6-position DIP switch controls the configuration address and FPGA configuration
mode.

The three leftmost switches choose one of eight possible configuration addresses. These
three DIP switches provide the System ACE controller and the CPLD the possibility of
using up to eight different configuration images as set by these three switches. The
Platform Flash memory supports up to four different images.

The three rightmost DIP switches set the FPGA configuration mode pins M2, M1, and M0
as shown in

32. Encryption Key Battery

An onboard battery holder is connected to the V

BATT

pin of the FPGA to hold the

encryption key for the FPGA. A 12-mm lithium coin battery (3V), such as Panasonic part
numbers BR1216, CR1216, and BR1225, or any other appropriate 12-mm lithium coin
battery (3V) can be used.

33. Configuration Source Selector Switch

The configuration source selector switch (SW12) selects between System ACE, Platform
Flash, and linear flash/CPLD methods of programming the FPGA. Whichever method is
selected to program the FPGA, make sure the FPGA configuration mode switches are set
appropriately for the desired method of configuration. The PC4 connector allows JTAG
download and debug of the board regardless of the setting of the configuration source
selector switch.

Table 15:

Configuration Mode DIP Switch Settings

M2

M1

M0

Mode

0

0

0

Master Serial

1

1

1

Slave Serial

0

1

1

Master Parallel (SelectMAP)

1

1

0

Slave Parallel (SelectMAP)

1

0

1

JTAG

www.BDTIC.com/XILINX

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Содержание M401

Страница 1: ...R ML401 ML402 ML403 Evaluation Platform User Guide UG080 v2 5 May 24 2006 www BDTIC com XILINX...

Страница 2: ...TS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN...

Страница 3: ...ections Minor edits to text for clarity 11 15 05 2 2 Clarified ZBT synchronous RAM size in Features section 01 13 06 2 3 Minor edits Deleted P N 0402337 obsolete from document s identification Deleted...

Страница 4: ...ML401 ML402 ML403 Evaluation Platform www xilinx com UG080 v2 5 May 24 2006 www BDTIC com XILINX...

Страница 5: ...Active High 18 8 User Push Buttons Active High 19 9 CPU Reset Button Active Low 19 10 Expansion Headers 20 11 Stereo AC97 Audio Codec 24 12 RS 232 Serial Port 24 13 16 Character x 2 Line LCD 24 14 IIC...

Страница 6: ...gram Switch 30 31 Configuration Address and Mode DIP Switches 30 32 Encryption Key Battery 30 33 Configuration Source Selector Switch 30 Configuration Options 31 JTAG Parallel Cable IV Cable and Syste...

Страница 7: ...at http www xilinx com literature index htm To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www x...

Страница 8: ...sign_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has bee...

Страница 9: ...ock output pair with SMA connectors One 100 MHz clock oscillator socketed plus one extra open 3 3V clock oscillator socket General purpose DIP switches ML401 ML402 platform LEDs and push buttons Expan...

Страница 10: ...sit the corresponding Web page ML401 http www xilinx com ml401 ML402 http www xilinx com ml402 ML403 http www xilinx com ml403 The information includes Current version of this user guide in PDF format...

Страница 11: ...ontroller SEL MAP SLV SERIAL JTAG JTAG JTAG JTAG JTAG MSTR SERL I O Expansion Header USB Controller 10 100 1000 Enet PHY AC97 Audio CODEC 16 X 32 Character LCD CF PC DDR SDRAM DDR SDRAM RS 232 XCVR Vi...

Страница 12: ...gure 3 page 13 back The numbered sections on the pages following the figures contain details on each feature Note The ML402 and ML403 boards might differ slightly from the board shown Figure 2 Detaile...

Страница 13: ...Description R Note The label on the CompactFlash CF card shipped with your board might differ slightly from the one shown Figure 3 Detailed Description of Virtex 4 ML40x Evaluation Platform Components...

Страница 14: ...tMAP modes See the Configuration Options page 31 section for more information I O Voltage Rails The FPGA has 11 banks of which only the first 10 banks are used The last bank is powered but unused The...

Страница 15: ...Use of DCI will disable the use of GPIO LED 2 and 3 4 Not supported 5 Optional User must install resistors R224 and R225 to use DCI In bitgen the switch g DCIUpdateMode Quiet must also be used Note Us...

Страница 16: ...the DDR clock signal reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips DDR Loop Signal The DDR loop signal is a trace driven and then received back at the FPGA with...

Страница 17: ...oscillators and are powered by the 3 3V supply 5 LCD Brightness and Contrast Adjustment Turning potentiometer R1 adjusts the image contrast of the character LCD 6 DIP Switches Active High Eight gener...

Страница 18: ...o be used for signaling error conditions such as bus errors but can be used for any other purpose Note On the ML403 board the Error 2 LED is not installed Table 6 summarizes the LED definitions and co...

Страница 19: ...9 CPU Reset Button Active Low The CPU reset button is an active Low push button intended to be used as a system or user reset button This button is wired only to an FPGA I O pin so it can also be use...

Страница 20: ...ts The VCCIO of these signals can be set to 2 5V or 3 3V by setting jumper J16 Table 9 summarizes the differential connections on this expansion I O connector Table 9 Expansion I O Differential Connec...

Страница 21: ...nector Table 10 Expansion I O Single Ended Connections J6 Header Pin Label FPGA Pin J6 Pin 2 HDR1_28 AA24 J6 Pin 4 HDR1_42 V20 J6 Pin 6 HDR1_36 AC25 J6 Pin 8 HDR1_2 AC24 J6 Pin 10 HDR1_52 W25 J6 Pin 1...

Страница 22: ...on connector to allow additional IIC devices to be bused together If the expansion IIC bus is to be utilized the user must have the IIC pull up resistors present on the expansion card Bidirectional le...

Страница 23: ...on TCK J3 Pin 13 TDO N A Expansion TDO J3 Pin 14 TDI N A Expansion TDI J3 Pin 15 LED North E2 LED North J3 Pin 16 GPIO Switch North E7 GPIO Switch North J3 Pin 17 LED Center C6 LED Center J3 Pin 18 GP...

Страница 24: ...operate up to 115200 Bd An interface chip is used to shift the voltage level between FPGA and RS 232 signals Note The FPGA is only connected to the TX and RX data pins on the serial port Therefore ot...

Страница 25: ...ort P2 supports an external video monitor Table 13 lists each board and its corresponding video DAC chip Note Due to the reduced pin count on ML403 board s XC4VFX12 FPGA only the five most significant...

Страница 26: ...re programs the FPGA The board also features a System ACE failsafe mode In this mode if the System ACE controller detects a failed configuration attempt it automatically reboots back to a predefined c...

Страница 27: ...ial or parallel SelectMAP modes For FPGA configuration via the CPLD and flash the configuration selector switch SW12 must be set to the CPLD Flash position See the Configuration Options page 31 sectio...

Страница 28: ...Xilinx XCF32P Platform Flash Configuration Storage Device Xilinx XCF32P Platform Flash configuration storage device offers a convenient and easy to use configuration solution for the FPGA The Platfor...

Страница 29: ...5 mm barrel type plug center positive For applications requiring additional power such as the use of expansion cards drawing significant power a larger AC adapter might be required If a different AC a...

Страница 30: ...the FPGA configuration mode pins M2 M1 and M0 as shown in Table 15 32 Encryption Key Battery An onboard battery holder is connected to the VBATT pin of the FPGA to hold the encryption key for the FPG...

Страница 31: ...G connection to the JTAG chain allows a host PC to download bitstreams to the FPGA using the iMPACT software tool PC4 also allows debug tools such as the ChipScope Pro Analyzer or a software debugger...

Страница 32: ...ch the programming method being used by the Platform Flash memory The configuration source selector switch should be in the Plat Flash setting if the use of Platform Flash memory is desired When set c...

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