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16 www.xilinx.com ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
Detailed Description
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2. DDR SDRAM
The board contains 64 MB of DDR SDRAM using two Infineon HYB25D256160BT-7 (or
compatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit data
bus capable of running up to 266 MHz. All DDR SDRAM signals are terminated through
47
Ω
resistors to a 1.25V VTT reference voltage. The board is designed for matched length
traces across all DDR control and data signals except clocks and the DDR Loop trace (see
“DDR Clock Signal” and “DDR Loop Signal” ).
The board can support up to 256 MB of total DDR SDRAM memory if larger chips are
installed. An extra address pin is present on the board to support up to 1-Gb DDR chips.
DDR Clock Signal
The DDR clock signal is broadcast from the FPGA as a single differential pair that drives
both DDR chips. The delay on the clock trace is designed to match the delay of the other
DDR control and data signals. The DDR clock is also fed back to the FPGA to allow for
clock deskew using Virtex-4 DCMs. The board is designed so that the DDR clock signal
reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips.
DDR Loop Signal
The DDR loop signal is a trace driven and then received back at the FPGA with a delay
equal to the sum of the trace delays of the clock and DQS signals. This looped trace can be
used in high-speed memory controllers to help compensate for the physical trace delays
between the FPGA and DDR chips.
3. Differential Clock Input And Output With SMA Connectors
High-precision clock signals can be input to the FPGA using differential clock signals
brought in through 50
Ω
SMA connectors. This allows an external function generator or
other clock source to drive the differential clock inputs that directly feed the global clock
input pins of the FPGA. The FPGA can be configured to present a 100
Ω
termination
impedance.
A differential clock output from the FPGA is driven out through a second pair of SMA
connectors. This allows the FPGA to drive a precision clock to an external device such as a
piece of test equipment.
Table 3 summarizes the differential SMA clock pin connections.
Table 3: Differential SMA Clock Connections
Label Clock Name FPGA Pin
J10 SMA_DIFF_CLK_IN_N C12
J7 SMA_DIFF_CLK_IN_P C13
J8 SMA_DIFF_CLK_OUT_N D7
J9 SMA_DIFF_CLK_OUT_P D8
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