
14
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
Detailed Description
R
1. Virtex-4 FPGA
A Xilinx Virtex-4 FPGA is installed on the evaluation platform (the board):
♦
ML401: XC4VLX25-FF668-10
♦
ML402: XC4VSX35-FF668-10
♦
ML403: XC4VFX12-FF668-10
Configuration
The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master
SelectMAP, and Slave SelectMAP modes. See the
“Configuration Options,” page 31
section
for more information.
I/O Voltage Rails
The FPGA has 11 banks of which only the first 10 banks are used. The last bank is powered
but unused. The I/O voltage applied to each bank is summarized in
Table 1:
I/O Voltage Rail of FPGA Banks
FPGA Bank
I/O Voltage Rail
0
3.3V
1
3.3V
2
3.3V
3
2.5V
4
3.3V
5
2.5V
6
2.5V
7
User selectable as 2.5V or 3.3V using jumper J16
8
3.3V
9
a
a. Bank 9 and 10 are non-connected pins in the case of the ML403 with XC4VFX12-FF668.
3.3V
10
a
3.3V (Powered but I/O pins are not used)
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