
20
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
Detailed Description
R
10. Expansion Headers
The board contains expansion headers for easy expansion or adaptation of the board for
other applications. The expansion connectors use standard 0.1-inch headers. The
expansion connectors contain connections to single-ended and differential FPGA I/Os,
ground, 2.5V/3.3V/5V power, JTAG chain, and the IIC bus.
Differential Expansion I/O Connectors
Header J5 contains 16 pairs of differential signal connections to the FPGA I/Os. This
permits the signals on this connector to carry high-speed differential signals such as LVDS
data. All differential signals are routed with 100
Ω
differential trace impedance. Matched
length traces are used across all differential signals; consequently, these signals connect to
the FPGA I/O and can also be used as independent single-ended nets. The V
CCIO
of these
signals can be set to 2.5V or 3.3V by setting jumper J16.
summarizes the differential
connections on this expansion I/O connector.
Table 9:
Expansion I/O Differential Connections (J5)
Header Pin
(Diff Pair Pos)
Header Pin
(Diff Pair Neg)
Label
(Diff Pair Pos)
Label
(Diff Pair Neg)
FPGA Pin
(Diff Pair Pos)
FPGA Pin
(Diff Pair Neg)
J5, Pin 4
J5, Pin 2
HDR2_4
HDR2_2
AA18
Y18
J5, Pin 8
J5, Pin 6
HDR2_28
HDR2_26
Y19
W19
J5, Pin 12
J5, Pin 10
HDR2_20
HDR2_18
Y20
Y21
J5, Pin 16
J5, Pin 14
HDR2_12
HDR2_10
W23
W24
J5, Pin 20
J5, Pin 18
HDR2_8
HDR2_6
Y22
Y23
J5, Pin 24
J5, Pin 22
HDR2_60
HDR2_58
AA19
AA20
J5, Pin 28
J5, Pin 26
HDR2_56
HDR2_54
Y17
AA17
J5, Pin 32
J5, Pin 30
HDR2_52
HDR2_50
AB20
AC20
J5, Pin 36
J5, Pin 34
HDR2_36
HDR2_34
AE21
AD21
J5, Pin 40
J5, Pin 38
HDR2_16
HDR2_14
AE20
AD20
J5, Pin 44
J5, Pin 42
HDR2_64
HDR2_62
AD19
AC19
J5, Pin 48
J5, Pin 46
HDR2_48
HDR2_46
AC18
AB18
J5, Pin 52
J5, Pin 50
HDR2_24
HDR2_22
AF23
AE23
J5, Pin 56
J5, Pin 54
HDR2_44
HDR2_42
AF21
AF22
J5, Pin 60
J5, Pin 58
HDR2_32
HDR2_30
AF19
AF20
J5, Pin 64
J5, Pin 62
HDR2_40
HDR2_38
AF18
AE18
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