PZ-TIO Manual
Version 1.01
© 2022 XIA LLC
22
4.3 Clockprog
–
not yet implemented
Programs the clock PLL that buffers PTP or external clocks for FPGA and MMCX outputs. This
allows for generating an output clock of arbitrary frequency.
Functions performed
-
Program PLL for PTP and external clock
Arguments
: Mode (read and display, write to EEPROM, program PLL registers)
Mode 0: read and display registers
Mode 1: write current register contents to PROM memory
Mode 2: Input 25 MHz, output 25 MHz on Y1 (FPGA)
Mode 3: Input 25 MHz, output 25 MHz on Y1 (FPGA) and Y3 (External)
Mode 4: Input 25 MHz, output 50 MHz on Y1 (FPGA), Y2 (backplane), and Y3 (External)
Mode 5: Input 50 MHz, output 50 MHz on Y1 (FPGA), Y2 (backplane), and Y3 (External)
Output
: display current register settings
Restrictions
: Do not execute during a data acquisition
4.1 monitordaq
Template for monitoring Pixie-16 data acquisition. At this point, it runs for the time specified in
the settings file and periodically writes the status registers to file.
Functions performed
-
Read settings files
-
Reset counters in FPGA
-
Loop for requested time, save status to RS.csv periodically
Arguments
: None
Output
: RS.csv
Restrictions
: Do not execute runstats or cgistats while monitordaq is in progress
