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PIXIE-4 User’s Manual
V2.69
©
XIA
2015. All rights reserved.
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In a third scenario, it may be desirable to reject pulses that occur while a GATE signal is on (or
off). Usually this is a dedicated signal for each channel, for example derived from a BGO shield
around the detector. When the BGO shield sees a pulse, not all of the energy was deposited in
the detector, and therefore this event should be rejected. The GATE signal is thus coincident
with the rising edge of the detector pulse (give or take a cable delay), in contrast to the GFLT
function that contributes to the event validation a filter time after the rising edge.
Figure 7.3. Block and timing diagrams of the GATE and VETO circuitry in the trigger/filter
FPGA. If required by the user, pulses are validated only if VETO and/or GATEBIT are present
during validation. GATEBIT reflects the status of the GATE input at the time of the trigger either
directly or after a coincidence window is applied. Names highlighted in green are controlled by
the parameters in the Gate tab of the P
ARAMETER
S
ETUP
Panel.