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XIA Pixie-4 Express Скачать руководство пользователя страница 31

PIXIE-4 User’s Manual

V2.69

©

XIA

2015. All rights reserved.

xxxi

analog gain

and offset

14bit
ADC

analog gain

and offset

14bit
ADC

analog gain

and offset

14bit
ADC

analog gain

and offset

14bit
ADC

FPGA –

trigger,

pileup,

FIFO

FPGA –

trigger,

pileup,

FIFO

DSP

Interface

logic

MCA ,

List mode

memory

32 bit,

33MHz

PCI

PCI

I/O

(J1)

clock,

trigger

(J2)

Veto

Figure 5.1:

Functional block diagram of the Pixie-4 front-end data acquisition and signal processing

card.

5.1 Analog Signal Conditioning

Each analog input has its own signal conditioning unit. The task of this circuitry is to adapt the
incoming signals to the input voltage range of the ADC, which spans 2V. Input signals are
adjusted for offsets, and there is a computer-controlled gain stage of switched relays. This helps
to bring the signals into the ADC's voltage range and set the dynamic range of the channel. A
fine tuning of the gain is achieved by multiplying the calculated energy values with digital gain
factors in the digital signal processor (DSP).

The ADC is not a peak sensing ADC, but acts as a waveform digitizer. In order to avoid
aliasing, we remove the high frequency components from the incoming signal prior to feeding
it into the ADC. The anti-aliasing filter, an active Sallen-Key filter, cuts off sharply at the
Nyquist frequency, namely half the ADC sampling frequency.

Though the Pixie-4 can work with many different signal forms, best performance is to be
expected when sending the output from a charge integrating preamplifier directly to the Pixie-
4 without any further shaping.

5.2 Real-time Processing Units

The real time processing units (RTPUs), one per two channels, consist of a field programmable
gate array (FPGA) which also incorporates a FIFO memory for each channel. The data stream
from the ADCs is sent to these units at the full ADC sampling rate. Using a pipelined
architecture, the signals are processed at this high rate, without the help of the on-board DSP.

Note that the use of one RTPU for two channels allows sampling the incoming signal at twice
the regular ADC clock frequency. If both channels are fed the same input signal, the RTPU can
give the second ADC a clock with a 180 degree phase shift, thus sampling the signal twice in

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Содержание Pixie-4 Express

Страница 1: ...rnished by XIA is believed to be accurate and reliable However XIA assumes no responsibility for its use or for any infringement of patents or other rights of third parties which may result from its u...

Страница 2: ...ce 34 6 Theory of Operation 35 6 1 Digital Filters for ray Detectors 35 6 2 Trapezoidal Filtering in the Pixie 4 37 6 3 Baselines and Preamplifier Decay Times 38 6 4 Thresholds and Pile up Inspection...

Страница 3: ...complex hit patterns Data readout rates through the CompactPCI PXI backplane to the host computer can be over 100Mbytes s The PXI backplane is also used to distribute clocks and trigger signals betwee...

Страница 4: ...Synch Wired or SYNC signal distributed through PXI backplane to synchronize timers and run start stop to 50ns Veto Global logic level to suppress event triggering Channel Gate Individual GATE to supp...

Страница 5: ...ftware the following sequence is recommended users with embedded host computer skip to step 4 1 If you have a remote controller first install the driver software for the controller itself Otherwise sk...

Страница 6: ...e Pixie 4 software distribution contains 1 an installation program Setup exe 2 the Pixie 4 software in the folder XIA Pixie4 and its subfolders The Pixie 4 software can be installed by running its ins...

Страница 7: ...panels are called Its controls are organized in three groups Setup Run Control and Results In the Setup group the Start System button opens the START UP panel in case you need to reboot the modules T...

Страница 8: ...of the PARAMETER SETUP panel click on the Oscilloscope button This opens a graph that shows the untriggered signal input In the OSCILLOSCOPE panel click Refresh to update the display The pulses shoul...

Страница 9: ...f module parameters 6 Click on the Run Control tab set Run Type to 0x301 MCA Mode Poll time to 1 second and Run time to 30 seconds or so then click on the Start Run button Aspinning wheel will appear...

Страница 10: ...he slot numbers entered in the START UP panel However the Pixie module itself loses all programming when it is switched off When the Pixie module is switched on again all programmable components need...

Страница 11: ...ngs for all four channels of a module are shown in the same tab At the upper right is a control to select the module to address At the bottom of the panel is a More button which will make all advanced...

Страница 12: ...eeting these conditions has the effect of raising the effective threshold For a modeled behavior of the trigger you can open displays from the OSCILLOSCOPE and the LIST MODE TRACES panels that show tr...

Страница 13: ...a BGO shield VETO a signal distributed to all modules and channels but each channel is individually enabled to require or ignore this signal VETO is active during the validation of a pulse after pile...

Страница 14: ...to set the polling time period for checking if list mode data is available for readout and or run time is reached to specify the data file name a base name plus 4 digit run number that can be made to...

Страница 15: ...gger filter and energy filter computed from the traces in the oscilloscope repeat the action of the Refresh button until a pulse is captured This is useful for low count rates Fit the pulses in the OS...

Страница 16: ...ions use the Run Control tab of the PARAMETER SETUP panel 3 4 Results Group The Results group of the MAIN control panel displays the count rates of the current or most recent run Click Update to refre...

Страница 17: ...emory or from a mca file saved at the end of a run Spectrum analysis is limited to fitting peaks with a Gaussian and computing the peak resolution There are several options to define the fit range as...

Страница 18: ...ns data as the filters implemented in the module not the reduced rate sampled at the OSCILLOSCOPE S dT However unless long list mode traces are acquired or energy filters are short there may not be su...

Страница 19: ...Ge detector we suggest to use a flat top of 1 2 s For a small detector 20 efficiency a flat top of 0 8 s is a good choice For larger detectors flat tops of 1 2 s and 1 6 s will be more appropriate In...

Страница 20: ...value of that gives the best resolution Pixie users can also use the fit routines in the OSCILLOSCOPE to manually find the decay time through exponentially fitting the untriggered input signals Anoth...

Страница 21: ...to create file series described in section 3 6 1 can also be used to scan through a range of energy filter or decay time settings This is equivalent to starting an MCA run with initial settings stopp...

Страница 22: ...value defined in the File Series Scan panel If you omit to click this button the file series will begin with the current value this is useful to resume a file series Set Scan Run Conditions will set...

Страница 23: ...used to increment the MCA spectrum The run continues until the host computer stops data acquisition either by reaching the run time set in the Pixie Viewer or by a manual stop from the user the module...

Страница 24: ...data new events are rejected Whenever a new event occurs the DSP first checks if there is enough room left in the intermediate buffer then transfers the data from the FPGAs into its intermediate buff...

Страница 25: ...ith the first buffer readout of module 0 followed by first buffers of module 1 module 2 module N then the second buffers of modules 0 to N and so forth In readout mode 2 list mode runs are repeated 32...

Страница 26: ...ata buffer can be written by the DSP in a number of formats User code should access the three variables BUFHEADLEN EVENTHEADLEN and CHANHEADLEN in the configuration file of a particular run to navigat...

Страница 27: ...he method of data buffering i e if raw data is directed to the intermediate Level 1 buffer or directly to the linear buffer Offline analysis programs should therefore check the value of RUNTASK which...

Страница 28: ...ord Variable Description 1 CHAN_TRIGTIME Fast trigger time 2 CHAN_ENERGY Energy 4 2 3 Reconstruction of list mode time stamps As discussed above in list mode the Pixie 4 records time information in th...

Страница 29: ...ven though the correct time difference would only be 141 1e 6 75s If such large time differences can be known to be impossible from the physics of the experiment e g max time of flight delay or from t...

Страница 30: ...BUF_TIMEHI 3 If count rates are extremely low in the order of one count per minute or less the time counter may see multiple 32 bit rollovers events For example the run may have started at 3 153 1756...

Страница 31: ...DC is not a peak sensing ADC but acts as a waveform digitizer In order to avoid aliasing we remove the high frequency components from the incoming signal prior to feeding it into the ADC The anti alia...

Страница 32: ...sly being filled with waveform data from the ADC only stopped to avoid overwriting of data for valid events On a trigger the read pointer is positioned such that it points to the beginning of the puls...

Страница 33: ...trol and Status Register CSR in the interface logic also called communication FPGA The communication FPGA links the PCI slave with the DSP and the on board memory The host can read out the memory with...

Страница 34: ...inuous Instead it is a string of discrete values as shown in Figure 6 2 Figure 6 2 is actually just a subset of Figure 6 1 b in which the signal was digitized by a Tektronix 544 TDS digital oscillosco...

Страница 35: ...the filter lengths results in time variant the lengths vary from pulse to pulse or time invariant the lengths are the same for all pulses filters Traditional analog filters are time invariant The conc...

Страница 36: ...is implemented in the Pixie 4 according to Eqn 6 2 The result of applying such a filter with Length L 1 s and Gap G 0 4 s to a ray event is shown in Figure 6 3 The filter output is clearly trapezoidal...

Страница 37: ...as the electronic noise of the system a number which depends on the rise time of the filter used Riding on top of this noise the ray peaks contribute an additional noise term the Fano noise which aris...

Страница 38: ...he module 6 4 Thresholds and Pile up Inspection As noted above we wish to capture a value of Vx for each ray detected and use these values to construct a spectrum This process is also significantly di...

Страница 39: ...d a fast filter and a slow filter The fast filter is used to detect the arrival of rays the slow filter is used for the measurement of Vx with reduced noise at longer filter rise times The fast filter...

Страница 40: ...6 6 peaks 1 and 2 are sufficiently well separated so that the leading edge of peak 2 falls after the peak of pulse 1 Because the trapezoidal filter function is symmetrical this also means that pulse...

Страница 41: ...he FILTERRANGE parameter of the DSP has to be set to select a particular filter range 6 6 Dead Time and Run Statistics 6 6 1 Definition of dead times Dead time in the Pixie 4 data acquisition can occu...

Страница 42: ...T3 before T4 T4 T1 T1 T0 the filter dead time The FIFO dead time is ignored As a consequence of the pileup inspection there is a delay of one filter time between the rising edge of the pulse and the...

Страница 43: ...he waveform data of the second pulse can not be recorded Essentially the FIFO is dead for new events until the FPGA readout is complete This effect is usually more significant than the cases a and b a...

Страница 44: ...e can already begin while the first event is read out as long as it finishes after the DSP has completed the readout This means the DSP has a filter time minus coincidence window available for readout...

Страница 45: ...not counted during this time and when computing the input count rate the time lost has to be taken into account FTDT is thus purely a correction for the computation of the input count rate 6 Summary...

Страница 46: ...ts lost 1 e ICR 2 Td 1 2 2 7 24 Note 1 FIFO logic prevents overlap of second pulse with coincidence window and FPGA readout but only when waveforms are requested Additional dead time due to stopped FI...

Страница 47: ...spends roughly 2 4 s per pulse to compute the energy Processing events containing pulses from several channels has less overhead and is thus faster per pulse This rate is much higher than the maximum...

Страница 48: ...edge of the pulse However the VETO input can be routed to replace the GATE input with a user option c In a third class of application the acquisition may only be of interest when GATE or VETO are off...

Страница 49: ...transfer may have to wait until the host finished reading the external memory which means the acquisition is stopped and there will be dead time in addition to the 300 us transfer time Case b is pict...

Страница 50: ...most recent command to start a new run i e in list mode runs the start of the first spill The TOTAL TIME includes the time spent for run start initialization and host readout Thus it can be used toget...

Страница 51: ...ld divide the number of triggers counted FASTPEAKS by the difference LIVE TIME FTDT since triggers are not counted during FTDT SFDT slow filter dead time The slow filter dead time counts the time new...

Страница 52: ...TO are off there is an alternate GATE statistics mode to count GDT and livetimes In Gate statistics mode all time and rate counters except RUN TIME and TOTAL TIME are only active if GDT_ON is high Thi...

Страница 53: ...of Td very close to the pileup inspection time energy filter rise time plus energy filter flat top plus a few cycles Notes 1 Output pulse counters are updated whenever an event has been processed inpu...

Страница 54: ...attempt to independently account for the system dead time SFDT is designed to start at the moment of the trigger measure the time during which no second trigger can be processed and the first may be r...

Страница 55: ...k slave mode e PXI clock slave mode JP1 JP2 JP3 JP3 JP3 LOC OUT BUS BUS PXI Figure 7 1 Jumper Settings for different clock distribution modes of Revision B modules In a group of modules there will be...

Страница 56: ...0 line on the PXI backplane for other purposes 7 1 3 Bussed Clock Mode If there have to be gaps between a group of Pixie 4 modules the daisy chained clock distribution will not work since the chain is...

Страница 57: ...to all channels The channels then use the distributed fast triggers and event triggers instead of their own local triggers to capture data In this way one channel can cause data to be acquired at the...

Страница 58: ...ly to obtain energy estimates on piled up pulses Note that since the timing of the group trigger is not precise with respect to the non triggering pulse the energy reported is only a rough estimate It...

Страница 59: ...ie 4 modules can be set up to operate in this mode using the chassis control panel of the Pixie Viewer The PXI backplane buffering has to be set up with the tools provided by the chassis manufacturer...

Страница 60: ...un it will also drive the SYNC line low This will be detected in all other modules and in turn stop the data acquisition Note that if the run synchronization is not operating properly and there was a...

Страница 61: ...coincident with the rising edge of the detector pulse give or take a cable delay in contrast to the GFLT function that contributes to the event validation a filter time after the rising edge Figure 7...

Страница 62: ...takes place a filter time after the rising edge of the pulse but is optionally subject to the current status of the VETO input and or the status of the GATE input stretched by Gate Window and latched...

Страница 63: ...OUT input of any enabled module is high 3 3V The status of this line is read as part of the event acquisition and is stored in the list mode data It is also possible to send the hit status bit of cha...

Страница 64: ...coincidence window the time period in which delayed channels can contribute to the hit pattern is thus 66 13 ns If longer delays between channels are expected from the physics of the experiment this...

Страница 65: ...e TOKEN line is driven low logic 0 The module in slot 2 typically XIA s PXI PDM module uses the up to 48 bit hit pattern from up to 12 modules slots 3 14 to make an accept reject decision If the hit p...

Страница 66: ...either the local OR the global coincidence test is passed check global and local d the global test AND local tests from all master modules pass check global for all module and local adds to global for...

Страница 67: ...global test box for all modules and the local adds to global box for module 0 No PXI PDM is required 3 To require at least 3 channels to be active in all modules use a PDM module in slot 2 and set th...

Страница 68: ...over mode the spectrum length is fixed to 16K The clover binning mode applies all runs but in list mode runs no sum energy is reported in the list mode data The clover mode is enabled by setting the c...

Страница 69: ...er a Pixie module is installed in a slot of the chassis for the first time it is detected as new hardware even if Pixie modules have been installed in other slots previously Point Windows to the drive...

Страница 70: ...n Window s device manager as PLX Custom OEM PCI 9054 Board 32 or 64 If the PLX is missing it indicates driver version 4 1 is used A picture of the driver information reported by Windows is shown below...

Страница 71: ...usual pulse shape Verify the input jumpers are set to the correct termination When taking the signal directly from the PMT without a preamplifier the correct termination is usually 50 2 Missing peaks...

Страница 72: ...32x buffer or 16 16 double buffer mode avoid frequent updates of run statistics and spectra set the polling time to a small value 0 1 0 01 verify the number of events buffer is set to the maximum 9 B...

Страница 73: ...0 and dashed blue attenuation arrows Jumper reference PCB Label Function JPx01 ATTN Remove only if you require attenuation Attenuation will be 1 7 5 if JPx02 is set JPx02 50 Set for input impedance of...

Страница 74: ...not set LOC to IN Daisy Chained Clock Master Connect pins 2 and 3 of JP2 not set LOC to IN Daisy Chained Clock Repeater Not set set Left Bussed Clock Master Connect pins 2 and 3 of JP2 Connect pin1 JP...

Страница 75: ...rved 1C LBL10 Left neighbor Fast Trigger output chained OR 3C LBR8 Right neighbor reserved 18C TRIG5 Bussed Token 19C LBL3 Left neighbor Control data to PDM left 20C LBL0 Left neighbor Clock input 2D...

Страница 76: ...module is busy with run initialization has filled its I O buffer with data or is finished with the run 0x0040 Bit 6 Unused Reserved for future use 0x0080 Bit 7 Unused Reserved for future use 0x0100 B...

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