Hardware Reference Guide
SST-PFB3-ISA
30
Hardware
Register
Details
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.0, Document #: 715-0078, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
Bit and Value
Hex
Address
AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12
1 1 1 0 1 0 1 0 0xEA
0xEA000
1 1 1 0 1 1 0 0 0xEC
0xEC000
1 1 1 0 1 1 1 0 0xEE
0xEE000
1 1 1 1 0 0 0 0 0xF0 0xF0000
1 1 1 1 0 0 1 0 0xF2 0xF2000
1 1 1 1 0 1 0 0 0xF4 0xF4000
1 1 1 1 0 1 1 0 0xF6 0xF6000
1 1 1 1 1 0 0 0 0xF8 0xF8000
1 1 1 1 1 0 1 0 0xFA
0xFA000
1 1 1 1 1 1 0 0 0xFC
0xFC000
1 1 1 1 1 1 1 0 0xFE
0xFE000
Table 12: AddrMatch Register Bit Descriptions
Bit Name
Description
AM19 – AM12
AM19-AM12 represent the upper address match required to decode memory.
These bits select the base memory address, from 0xA0000 to 0xFE000. For example,
writing 0xD0 to this register selects 0xD0000 as the memory base address. Refer to
Table 11,
AddrMatch Register Values
, for more details.
If a 16K window size is selected, AM13-AM12 are ignored and 16K boundaries are
used for the memory address. As a result, only even-window boundaries may be
chosen. The card could be set to 0xD0000 or 0xD4000, but 0xD2000 would be invalid.
Refer to Table 17,
Winsize Register Values
, for information on bit usage with other window
sizes.