Hardware Reference Guide
SST-PFB3-ISA
26
Hardware
Register
Details
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.0, Document #: 715-0078, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
3.1 PFB3-ISA Card Configuration Registers
This chapter provides technical hardware information. The following information is intended for
programmers familiar with hardware-level PC programming.
3.1.1 Host Register Layout
The registers are located in I/O space. The base I/O address is set via the
DIP switch
.
Note
Upon card power up, or after a physical reset from the system, it
typically takes 1 second for the card to initialize (though it is
recommended that applications wait up to 2 seconds). Initialization can
be confirmed by monitoring the LEDs or by reading the FamilyID
register, as described in Section C.1.1,
Verifying Card Presence
.
Table 7: Host Register Layout
The following “offsets” are from the base address.
Offset
Name
7
6
5
4
3
2
1
0
00h Control
CardRun
(r/w)
MemEn
(r/w)
IntEn
(r/w)
WdTout
(read)
HostIrq1
(r/w)
HostIrq0
(r/w)
CardIrq1
(r/w)
CardIrq0
(r/w)
01h
AddrMatch
AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12
02h
BankAddress
BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12
03h
WinSize WS19 WS18 WS17 WS16 WS15 WS14 WS13 WS12
04h
HostIrq
(r/w)
X X X X
IrqLevel3
IrqLevel2 IrqLevel1 IrqLevel0
05
LedReg
(read)
X X X X
CommRed
CommGrn
SysRed
SysGrn
06h
Debug
(r/w)
HWReset X
X JTAGEN
CPUTRST
CPUTMS
CPUTDI
CPUTCK
07
HDR
(read)
HostDataReg (written by CPU)