SST-PFB3-ISA
Hardware Reference Guide
Hardware Register Details
33
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.0, Document #: 715-0078, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
3.1.5 WinSize Register
This register controls the window size by masking off the AM19-AM12 and BA19-12 bits in the
AddrMatch and Bank Address registers. Table 17,
Winsize Register Values
, maps the WS bit
values required for each valid window size.
Table 16: WinSize Register Settings
Bit
7
6
5
4
3
2
1
0
Name
WS19 WS18 WS17 WS16 WS15 WS14 WS13 WS12
Read/Write
R
R R/W R/W R/W R/W R/W R
Reset
0 0 0 0 0 0 1 1
Table 17: WinSize Register Values
In this table, the default window values are highlighted.
Bit and Value
Window
Size
Description
WS19
WS18
WS17
WS16
WS15
WS14
WS13
WS12
0 0 0 0 0 0 0 1 8K
AM19-AM13
used,
AM12 ignored
BA19-BA13 used,
BA12 ignored
0
0
0
0
0
0
1
1
16K
AM19-AM14 used,
AM13-AM12 ignored
BA19-BA14 used,
BA13-BA12 ignored
0 0 0 0 0 1 1 1 32K
AM19-AM15
used,
AM14-AM12 ignored
BA19-BA15 used,
BA14-BA12 ignored
0 0 0 0 1 1 1 1 64K
AM19-AM16
used,
AM15-AM12 ignored
BA19-BA16 used,
BA15-BA12 ignored
0 0 0 1 1 1 1 1 128K
AM19-AM17
used,
AM16-AM12 ignored
BA19-BA17 used,
BA16-BA12 ignored
0 0 1 1 1 1 1 1 256K
AM19-AM18
used,
AM17-AM12 ignored
BA19-BA18 used,
BA17-BA12 ignored