SST-PFB3-ISA
Hardware Reference Guide
Hardware Register Details
27
©2004 Woodhead Software & Electronics, Division of Woodhead Canada Limited
Document Edition: 1.0, Document #: 715-0078, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
3.1.2 Control Register
This register is a group of control and status bits.
Table 8: Control Register Settings
Bit
7
6
5
4
3
2
1
0
Name
CardRun MemEn IntEn WdTout HostIrq1 HostIrq0 CardIrq1 CardIrq0
Read/Write
R/W R/W R/W R R/W R/W R/W R/W
Reset
0 0 0 0 0 0 0 0
The card has four interrupt flags, two for use in each direction. Setting CardIrq1 or CardIrq0
generates an interrupt to the card with the relevant flag set. When HostIrq1 OR HostIrq0 is '1'
and IntEn is '1', the card drives the IRQ pin (as set by IrqLevel) high.
One flag could be used for a command interface, and another for changing I/O data.
The firmware module dictates how these flags are used. If the module uses only one flag,
it will be Flag 0.
Table 9: Control Register Bit Descriptions
Bit Name
Description
CardRun
This bit controls and indicates whether or not the card’s processor is running.
It also affects the Sys LED.
•
When this bit is 0, the processor is halted, and the LED is RED
•
When this bit is 1, the processor is running normally, and the LED is under card
processor control
•
When this bit is 1, and watchdog has timed out, processor is halted, and the LED is
RED
•
This bit must remain low for at least 50
µ
s to guarantee proper reset
MemEn
This bit indicates and controls whether or not the card’s shared memory will respond to host
memory accesses. This may be used to multiplex several SST-PFB3-ISA cards at the same
base address. MemEn high (‘1’) enables shared memory decoding of addresses in this
board’s range.
IntEn
•
Writing 1 enables interrupts
•
Writing 0 disables interrupts (the HostIrq flags still function as described)
WdTout
WdTout high (‘1’) indicates that a watchdog timeout has occurred, or that the card’s
processor has been held in RESET by some other means. To restore this bit to 0, clear
CardRun.
HostIrq1
•
This bit is used by the card’s processor to send interrupts to interrupt flag 1 of the host.
•
Writing 1 acknowledges the interrupt and clears it
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
