W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 68 -
8.16 Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3L SDRAM, even if the rest of the
system is powered down. When in the Self-Refresh mode, the DDR3L SDRAM retains data without
external clocking. The DDR3L SDRAM device has a built-in timer to accommodate Self-Refresh
operation. The Self-Refresh-Entry (SRE) Command is defined by having CS#, RAS#, CAS#, and CKE
held low with WE# high at the rising edge of the clock.
Before issuing the Self-Refresh-Entry command, the DDR3L SDRAM must be idle with all bank
precharge state with t
RP
satisfied. ‘Idle state’ is defined as all banks are closed (t
RP
, t
DAL
, etc.
satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are
satisfied (t
MRD
, t
MOD
, t
RFC
, t
ZQ
init, t
ZQ
oper, t
ZQCS
, etc.) Also, on-die termination must be turned off
before issuing Self-Refresh-Entry command,
by either registering ODT pin low “ODTL + 0.5t
CK
” prior
to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry
command is registered, CKE must be held low to keep the device in Self-Refresh mode. During
normal operation (DLL on), MR1 (A0 = 0), the DLL is automatically disabled upon entering Self-
Refresh and is automatically enabled (including a DLL-Reset) upon exiting Self-Refresh.
When the DDR3L SDRAM has entered Self-Refresh mode, all of the external control signals, except
CKE
and RESET#, are “don't care.” For proper Self-Refresh operation, all power supply and reference
pins (V
DD
, V
DDQ
, V
SS
, V
SSQ
, V
REFCA
and V
REFDQ
) must be at valid levels. V
REFDQ
supply may be
turned OFF and V
REFDQ
may take any value between V
SS
and V
DD
during Self Refresh operation,
provided that V
REFDQ
is valid and stable prior to CKE going back High and that first Write operation or
first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. The
DRAM initiates a minimum of one Refresh command internally within t
CKE
period once it enters Self-
Refresh mode.
The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that
the DDR3L SDRAM must remain in Self-Refresh mode is t
CKESR
. The user may change the external
clock frequency or halt the external clock t
CKSRE
after Self-Refresh entry is registered, however, the
clock must be restarted and stable t
CKSRX
before the device can exit Self-Refresh operation.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable
prior to CKE going back HIGH. Once a Self-Refresh Exit command (SRX, combination of CKE going
high and either NOP or Deselect on command bus) is registered, a delay of at least t
XS
must be
satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for
any internal refresh in progress. Before a command that requires a locked DLL can be applied, a delay
of at least t
XSDLL
must be satisfied.
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration
commands may be required to compensate for the voltage and temperature drift as described in
section 8.18
on page 78. To issue ZQ calibration commands,
applicable timing requirements must be satisfied (See Figure 72 -
on page
79).
CKE must remain HIGH for the entire Self-Refresh exit period t
XSDLL
for proper operation except for
Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3L SDRAM can be put back into Self-
Refresh mode after waiting at least t
XS
period and issuing one refresh command (refresh period of
t
RFC
). NOP or deselect commands must be registered on each positive clock edge during the Self-
Refresh exit interval t
XS
. ODT must be turned off during t
XSDLL
.
