W632GU6NB
Publication Release Date: Aug. 20, 2018
Revision: A01
- 125 -
Basic IDD and IDDQ Measurement Conditions, continued
SYM.
DESCRIPTION
I
DD4R
Operating Burst Read Current
CKE:
High;
External clock:
On;
t
CK
, CL:
see Table 38;
BL:
8
(1,6)
;
AL:
0;
CS#:
High between RD;
Command, Address, Bank Address Inputs:
partially toggling according to Table 44;
Data IO:
seamless read data burst with different data between one burst and the next one according to Table
44;
DM:
stable at 0;
Bank Activity:
all banks open, RD commands cycling through banks:
0,0,1,1,2,2,... (see Table 44);
Output Buffer and R
TT
:
Enabled in Mode Registers
(2)
;
ODT Signal:
stable at 0;
Pattern Details:
see Table 44
I
DDQ4R
Operating Burst Read I
DDQ
Current
Same definition like for I
DD4R
, however measuring I
DDQ
current instead of I
DD
current
I
DD4W
Operating Burst Write Current
CKE:
High;
External clock:
On;
t
CK
, CL:
see Table 38;
BL:
8
(1)
;
AL:
0;
CS#:
High between WR;
Command, Address, Bank Address Inputs:
partially toggling according to Table 45;
Data IO:
seamless write data burst with different data between one burst and the next one according to
Table 45;
DM:
stable at 0;
Bank Activity:
all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... (see Table 45);
Output Buffer and R
TT
:
Enabled in Mode Registers
(2)
;
ODT Signal:
stable at HIGH;
Pattern Details:
see Table 45
I
DD5B
Burst Refresh Current
CKE:
High;
External clock:
On;
t
CK
, CL, nRFC:
see Table 38;
BL:
8
(1)
;
AL:
0;
CS#:
High between
REF;
Command, Address, Bank Address Inputs:
partially toggling according to Table 46;
Data
IO:
MID-LEVEL;
DM:
stable at 0;
Bank Activity:
REF command every nRFC (see Table 46);
Output Buffer and R
TT
:
Enabled in Mode Registers
(2)
;
ODT Signal:
stable at 0;
Pattern Details:
see Table 46
I
DD6
Self Refresh Current: Normal Temperature Range
Auto Self-Refresh (ASR):
Disabled
(4)
;
Self-Refresh Temperature Range (SRT):
Normal
(5)
;
CKE:
Low;
External clock:
Off;
CK and CK#:
LOW;
CL:
see Table 38;
BL:
8
(1)
;
AL:
0;
CS#, Command,
Address, Bank Address, Data IO:
MID-LEVEL;
DM:
stable at 0;
Bank Activity:
Self-Refresh
operation;
Output Buffer and R
TT
:
Enabled in Mode Registers
(2)
;
ODT Signal:
MID-LEVEL
I
DD6ET
Self-Refresh Current: Extended Temperature Range
Auto Self-Refresh (ASR):
Disabled
(4)
;
Self-Refresh Temperature Range (SRT):
Extended
(5)
;
CKE:
Low;
External clock:
Off;
CK and CK#:
LOW;
CL:
see Table 38;
BL:
8
(1)
;
AL:
0;
CS#,
Command, Address, Bank Address, Data IO:
MID-LEVEL;
DM:
stable at 0;
Bank Activity:
Extended Temperature Self-Refresh operation;
Output Buffer and R
TT
:
Enabled in Mode
Registers
(2)
;
ODT Signal:
MID-LEVEL
I
DD7
Operating Bank Interleave Read Current
CKE:
High;
External clock:
On;
t
CK
, nRC, nRAS, nRCD, nRRD, nFAW, CL:
see Table 38;
BL:
8
(1,6)
;
AL:
CL-1;
CS#:
High between ACT and RDA;
Command, Address, Bank Address Inputs:
partially toggling according to Table 47;
Data IO:
read data bursts with different data between one
burst and the next one according to Table 47;
DM:
stable at 0;
Bank Activity:
two times interleaved
cycling through banks (0, 1, ...7) with different addressing, see Table 47;
Output Buffer and R
TT
:
Enabled in Mode Registers
(2)
;
ODT Signal:
stable at 0;
Pattern Details:
see Table 47
I
DD8
RESET# Low Current
RESET#:
Low;
External clock:
Off;
CK and CK#:
Low;
CKE:
FLOATING;
CS#, Command,
Address, Bank Address, Data IO:
FLOATING;
ODT Signal:
FLOATING
RESET# Low current reading is valid once power is stable and RESET has been Low for at least
1mS
Notes:
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00b.
2. Output Buffer Enable: set MR1 A[12] = 0b; set MR1 A[5,1] = 01b; Rtt_Nom enable: set MR1 A[9,6,2] = 011b; Rtt_WR
enable: set MR2 A[10,9] = 10b.
3. Precharge Power Down Mode: set MR0 A12=0b for Slow Exit or MR0 A12=1b for Fast Exit.
4. Auto Self-Refresh (ASR): set MR2 A6 = 0b to disable or 1b to enable feature.
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0b for normal or 1b for extended temperature range.
6. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0b.
