Counter Module 750-404
10
:$*2
⇓
,
2
⇓
6<67(0
Functional description
The counter module acquires the time between one or more rising edges of the CLOCK
input signal and calculates the frequency of the applied signal.
The calculation and process image update are initiated every 1
st
, every 4
th
or every 16
th
rising edge depending on the integration time selected via the CONTROL byte. The first
detection of a rising edge starts the cyclic period measurement and cannot provide a
valid frequency value. In this case the module will send 0xFFFFFFFF
H
for input
information. The same input value is returned when a static high or static low signal is
applied to the CLOCK input.
If there are no signal changes seen at the CLOCK input, the module can be forced to
update the process image after defined parameterizable time spans. In this state the
module will send the non valid value 0xFFFFFFFF
H
too.
The following figures illustrate a process data cycle.
,1387)5(4
'$7$9$/,'
352&(66'$7$
7
3
7
[))))))))
[))))))))
''
'' ''
''
''
7
3
I FXUUHQWSHULRG
7
0D[LPXPGDWDKROGWLPHSDUDPHWHUL]DEOH
,QSXW'DWD
''
Figure 2: Timing diagram for process data update sequence
(integration time = 1 period)
,1387)5(4
'$7$9$/,'
352&(66'$7$
7
3
7
7
3
I FXUUHQWSHULRG
7
0D[LPXPGDWDKROGWLPHSDUDPHWHUL]DEOH
,QSXW'DWD
''
[))))))))
''
[))))))))
''
Figure 3: Timing diagram for process data update sequence
(integration time = 4 periods)
