Visual Circuits ReelTime 4, Руководство пользователя

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Appendix
58
Theory of Operation
(See Block Diagram of Board on page 60 for the following
description)
The board consists of a PCI bus-mastering bridge chip and four
identical MPEG2 decoder channels. The key to understanding the
operation of the board and the driver is to understand the buffer
management. There is a small FIFO buffer in the PCI bridge chip
to allow for PCI bus latencies, a buffer allocated by the driver in
host memory dedicated to each channel, and a buffer on the board
for each channel. The memory buffer on the board is divided into a
not-yet-decoded raw data section, a section for the decoded video,
and a section for the decoded audio (often referred to as the
payload buffers). There is also a section for the OSD data, and an
optional VBI data area. The rest of the memory is taken up by a
combination of decoding and display areas. This is where the
picture is reconstructed and displayed. All these memory areas are
defined in the software. The data and payload memory are circular
buffers, and the driver reads these pointers into these buffers to
determine how much data the channel needs. The minimum and
maximum size of data delivered to the data buffers are set as a
driver parameter.
When a file is loaded, data is transferred from the disk into the
memory buffer for the channel and into the memory data area on
the board (until it is full). When a start command is issued, the
data is demultiplexed and transferred into the payload areas.
Reconstruction and display begin after a few frames are received.
From then on, the driver monitors the state of the data buffer on the
board for each channel, decides which channels most needs to be
fed data, and transfers a portion of data from the host memory
buffer to the data buffer for that channel. Only one channel at a
time can be serviced. The data transfer rate is fixed at 5.5mbytes
per second. The data buffer “drains out” at a speed dependent on
the bitrate of the file.