VIPA CPU 21 Series, Руководство пользователя

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Chapter 5 Deployment CPU 21x-2BT02 with H1 / TCP/IP Manual VIPA CPU 21x
5-18 HB103E - Rev. 05/45
To enable the PLC to process connection requests, it requires an active
PLC application program on the CPU. This uses the handling blocks
(SEND, RECEIVE, ...) that are included in the CPU 21x-2BT02 amongst
others.
The PLC program also requires that a communication channel between the
CPU and the CP ("synchronization") is specified first. This function is
performed by the SYNCHRON block.
Transmission and reception is initiated by means of SEND and RECEIVE.
A data transfer is initiated by means of SEND_ALL or RECEIVE_ALL.
Error messages will appear in the indicator word.
The used interface of the CP has to be synchronized in the start-up OB OB
100 by means of the handling block SYNCHRON.
After power is turned on, the CPU21x-2BT02 requires app. 15s for the boot
procedure. If the PLC should issue a request for synchronization during
this time, an error is returned in the configuration error byte PAFE. This
message is removed when the CP module has completed the boot
process.
The timer in this block is initially set to 20s. Processing will be stopped if
the synchronization is not completed properly within this period.
The following table shows the available block sizes.
Block size CP Block size in Byte
0 Default
1 16
2 32
3 64
4 128
5 256
6 512
255 512
The sending and receiving blocks SEND and RECEIVE which initiate the
send and receive operations must be configured in the cycle program OB1.
The blocks SEND_ALL and RECEIVE_ALL perform the actual data-
transfer.
Purely passive connections only require the components SEND_ALL or
RECEIVE_ALL.
To protect the data transfer you should integrate various checkpoints that
evaluate the indicator word.
PLC application
programming
Synchronization
Block sizes
Cycle