VIPA CPU 21 Series, Руководство пользователя

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Manual VIPA CPU 21x Chapter 5 Deployment CPU 21x-2BT02 with H1 / TCP/IP
HB103E - Rev. 05/45 5-3
Ethernet supports the principle of random bus accesses: every station on
the network accesses the bus independently as and when required. These
accesses are coordinated by a CSMA/CD (Carrier Sense Multiple Ac-
cess/Collision Detection) scheme: every station “listens” on the bus cable
and receives communication messages that are addressed to it.
Stations will only initiate a transmission when the line is unoccupied. In the
event that two participants should start transmitting simultaneously, they
will detect this and stop transmitting to restart after a random delay time
has expired.
The internal CP of the CPU 21x-2BT02 is directly connected to the CPU
21xNET by means of a Dual-Port-RAM. The Dual-Port-RAM is divided into
4 equal segments called page frames.
These 4 page frames are available at the CPU as standard CP interface.
Data is exchanged by means of standard handler blocks (SEND and
RECEIVE).
H1 and TCP/IP communication is controlled by means of connections that
are defined with the VIPA configuration tool WinNCS and are directly
transferred into the CPU via the twisted-pair connection.
For details on the configuration refer to the WinNCS manual (HB91).
CPU 21x NET
CP CPU
Connections
configured
with WinNCS
Ethernet
additional interfaces
data
HTBs
Application
program
(SEND, RECEIVE)
Frames
Hub
Frames
VIPA Rack-135U
CP 143 H1 / TCP/IP
System 200V
CPU 21x NET
Frames
Frames
Access control
Communication