VL-12CT96/7 Analog & Digital I/O Card
4-7
Analog Input Data Low Register
ADCLO — 0303H (8-Bit mode)
— 0304H (16-Bit mode)
7
6
5
4
3
2
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 4-10. A/D Data Low Register
The ADCLO register is a read register containing the lower 8 bits of data from the A/D conversion
results. It is used in conjunction with the ADCHI register to read the complete 12- or 16-bit data word.
After a conversion is complete (as reported by the Done bit in the STATUS register) the ADCLO register
should be read first, followed by the ADCHI register. A word-wide input instruction from the ADCLO
register (in ax,dx) will fetch data from both registers in the proper sequence. This is true for both 8-
bit and 16-bit modes as determined by jumper V8[1-2].
In 8-bit mode, the ADCHI and ADCLO registers are mapped to correspond with Analog Device’s RTI-
1265 board. In 16-bit mode, the data registers are moved to an even address boundary to facilitate
efficient single-cycle reading of the A/D data.
D7-D0 — A/D Input Data (Least Significant Byte).
These bits contain data bits D7 through D0 of the
conversion results. See the A/D Data Representation section on page 4-8 for a discussion of data format.
Analog Input Data High Register
ADCHI — 0304H (8-Bit mode)
— 0305H (16-Bit mode)
7
6
5
4
3
2
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 4-11. A/D Data High Register
The ADCHI register is a read register containing the upper 8 bits of data from the A/D conversion
results. It is used in conjunction with the ADCLO register to read the complete 12- or 16-bit data word.
On the VL-12CT96, bit D
3
is duplicated (sign extended) into bits D
4
through D
7
.
When reading data, the ADCLO register should be read first, followed by the ADCHI register. See the
A/D Data Low Register section above for further information on register access.
When the ADCHI register is read the following events occur:
• The Done bit in the STATUS register is reset to “0.”
• The A/D interrupt request signal goes inactive if A/D interrupts are enabled.
• The next channel in sequence is selected if auto-increment mode enabled.
• A new A/D conversion is triggered if auto-trigger mode is enabled.
D7-D0 — A/D Input Data (Most Significant Byte).
These bits contain data bits D15 through D8 of the
conversion results.
Registers — Analog Input Registers
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