VL-12CT96/7 Analog & Digital I/O Card
4-3
(00)—Channels 0 to 15.
This selection does not restrict the number of channels accessed in auto-
increment mode. (00) should be selected for applications which do not use auto-increment mode.
(10)—Channels 0 to 7.
This selection causes the first eight channels to be accessed in auto-increment
mode. Channels 0 through 7 are accessed in sequence, and then repeated (modulo 8 restriction of
the value contained in the SELECT register).
(11)—Channels 0 to 3.
This selection causes the first four channels to be accessed in auto-increment
mode. Channels 0 through 3 are accessed in sequence, and then repeated (modulo 4 restriction of
the value contained in the SELECT register).
D4 — Auto Increment Enable.
Setting this bit to “1” places the VL-12CT96/7 in auto-increment mode. In
this mode the SELECT register increments by one after the ADCHI register is read, allowing the next
channel in sequence to be converted. The SELECT register will increment to a maximum value set
by the Scan Range Limit (bits D
6
and D
5
of this register) and then repeat starting again with channel
0. A settling delay set by jumper V7 is inserted after each increment. Resetting this bit to “0” disables
auto-increment mode, allowing the SELECT register to retain its value. Auto-increment is disabled
upon board reset. Auto-increment is compatible with manual and auto-trigger modes.
Before selecting auto-increment mode, the initial channel to be converted (usually channel 0) should
be selected by writing to the SELECT register.
D3 — Auto Trigger Enable.
Setting this bit to “1” places the VL-12CT96/7 in auto-trigger mode. In this
mode a new A/D conversion is triggered immediately after the ADCHI register is read, eliminating the
need to trigger a conversion by writing to the CONVERT register.
There are two ways to trigger an A/D conversion: writing to the CONVERT register or reading the
ADCHI register (if auto-trigger is enabled).
To use auto-triggering, set this bit to “1,” start the first A/D “manually” by writing to the CONVERT
register, wait until Done, then read the ADCLO and ADCHI registers. From this point on, just wait
until Done and read data.
D2 — Not Used.
This bit has no function on the VL-12CT96/7.
D1 — Parallel Port Interrupt Enable.
Setting this bit to “1” enables parallel port interrupts. In this mode
an interrupt request is sent to the CPU when specific parallel port signal conditions are met as
determined by jumper V13. Reset this bit to “0” to disable interrupt requests from the parallel port.
See page 5-4 for further information about operating the parallel port with interrupts. An interrupt
software example is shown on page 6-8.
D0 — A/D Interrupt Enable.
Setting this bit to “1” enables A/D interrupts. In this mode an interrupt
request is sent to the CPU when the A/D conversion is complete. Reset this bit to “0” to disable interrupt
requests from the A/D converter. See page 5-2 for further information about operating the A/D
converter with interrupts. An interrupt software example is shown on page 6-2.
Registers — Analog Input Registers
Содержание VL-12CT96
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