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Map and Paging Control Register 

 

 

Map and Paging Control Register 

MPCR (READ/WRITE) 00E3H (or 01E3h via CMOS Setup) 

 

D7 D6 D5 D4 D3 D2 D1 D0 

FPGEN 

DOCEN1 

DOCEN0 

SB-SEL 

VB-SEL 

PG2 PG1 PG0 

 

Table 22: Map and Paging Control Register Bit Assignments 

Bit Mnemonic Description 

D7 FPGEN 

FLASH Paging Enable — Enables a 64K page frame from E0000h to 
EFFFFh. Used to gain access to the on-board FLASH memory. 

FPGEN = 0 

FLASH page frame disabled. 

FPGEN = 1 

FLASH page frame enabled. 

D6-D5 DOCEN1-

DOCENO 

DiskOnChip Enable — Enables a 8K page frame used to gain access to the 
Disk on Chip. 

   

 

  Memory Range within 

 PG2 

PG1   DiskOnChip  

  0 0 

Disabled 

 0 

1 

D000:0 

 1 

0 

D800:0 

 1 

1 

DE00:0 

D4 SB-SEL 

System BIOS Selection — Indicates the status of jumper VS2[1-2]. 

SB-SEL = 0 

Jumper out, Secondary System BIOS selected. 

SB-SEL = 1 

Jumper in, Primary System BIOS selected. 

Note!  This is a read-only bit

 

D3 VB-SEL 

Video BIOS Selection — Indicates the status of jumper VS2[3-4]. 

VB-SEL = 0 

Jumper out, Secondary System BIOS selected. 

VB-SEL = 1 

Jumper in, Primary System BIOS selected. 

Note!  This is a read-only bit

 

D2-D0 PG2-PG0 Page Select — Selects which 64K block of FLASH will be mapped into the page 

frame at E0000h to EFFFFh 

   

 

 

Memory Range within 

 PG2 

PG1  PG0 

FLASH  

 

0 0 0 000000h 

to 

00FFFFh 

 

0 0 1 010000h 

to 

01FFFFh 

 

0 1 0 020000h 

to 

02FFFFh 

 

0 1 1 030000h 

to 

03FFFFh 

 

1 0 0 040000h 

to 

04FFFFh 

 

1 0 1 050000h 

to 

05FFFFh 

 

1 1 0 060000h 

to 

06FFFFh 

 

1 1 1 070000h 

to 

07FFFFh

 

 

44 – Reference 

EPM-CPU-10 Reference Manual 

Содержание EPM-CPU-10

Страница 1: ...Reference Manual EPM CPU 10 Pentium III Celeron processor module with 10 100 Ethernet Video and PC 104 Plus interface ...

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Страница 3: ...EPM CPU 10 Pentium III Celeron processor module with 10 100 Ethernet Video and PC 104 Plus interface MEPM CPU 10 ...

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Страница 5: ...M CPU 10 Support Page at http www versalogic com private jaguarsupport asp contains additional information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and manufacturers links for chips used in this product BIOS information and upgrades Utility routines and benchmark software Note This is a private page for EPM C...

Страница 6: ......

Страница 7: ...eserved Notice Although every effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify an...

Страница 8: ......

Страница 9: ... Assembly 10 Stack Arrangement 10 External Connectors 11 Connector Location Diagrams 11 Connector Functions and Interface Cables 12 High Density 80 Pin Cable JS4 13 High Density 80 Pin Cable JS3 14 Jumper Block Locations 15 Jumper Summary 16 Jumper Summary 17 Power Supply 18 Power Connectors 18 Power Requirements 19 Lithium Battery 19 CPU 20 Processor Replacement 20 Processor Side Bus Selection 20...

Страница 10: ...t Connector 31 Flat Panel Display Connector 32 Compatible Flat Panel Displays 33 Flat Panel Display Selection 33 Flat Panel Power 33 Ethernet Interface 34 Ethernet Connector 34 Ethernet Status 34 Watchdog Timer 35 Enabling the Watchdog 35 Refreshing the Watchdog 35 CPU Temperature Monitor 35 USB1 1 Interface 36 Expansion Bus 37 PC 104 Plus 37 PC 104 37 I O Configuration 37 Memory and I O Map 38 Me...

Страница 11: ...cements Ethernet Remote boot capable Single supply 5V operation Latching I O connectors Customizing available Fanless option TVS devices Customizable setup defaults The EPM CPU 10 is a complete computer system in a compact two board set It may be used alone or with expansion modules It features a PC 104 Plus expansion interface for fast PCI based interface to a wide variety of PC 104 and PC 104 Pl...

Страница 12: ...riggers The EPM CPU 10 socket 370 compliant 2 board computer will accept Intel Flip Chip Pentium and Intel Flip Chip Celeron Chips Processors speeds up to 850 MHz are available This exceptional processor card was designed from the ground up for OEM applications with longevity and reliability as the focus It is fully supported by the VersaLogic design team Both hardware and software BIOS customizat...

Страница 13: ...terface One 32 pin JEDEC DIP socket Accepts one DiskOnChip device Height limit of 0 330 Video Interface Intel C T 69030 chip 4 MB VRAM Resolutions to 1600 x 1200 Supports up to 36 bit flat panel displays IDE Interface One PCI based IDE channel 40 pin interface compatble with enhanced IDE mode 4 and Ultra DMA only Supports up to two IDE devices hard drives CD ROM etc Floppy Disk Interface Supports ...

Страница 14: ... name of a technician or engineer who we can contact if we have questions Quantity of items being returned The model and serial number bar code of each item A description of the problem Steps you have taken to resolve or repeat the problem The return shipping address Warranty Repair All parts and labor charges are covered including return shipping charges for UPS 3rd Day Select delivery to United ...

Страница 15: ...tatic foam pad if available The board should also be protected during shipment or storage by keeping inside a closed metallic anti static envelope Note The exterior coating on some metallic anti static bags is sufficiently conductive to cause excessive battery drain if the bag comes in contact with the bottom side of the EPM CPU 10 LITHIUM BATTERY Warning To prevent shorting premature failure or d...

Страница 16: ...AM module into the SODIMM socket Latch into place CABLES PERIPHERAL DEVICES Plug video adapter cable p n VL CBL 1007 into socket JN2 and attach video monitor Plug keyboard into socket JS4 JC Plug floppy data connector JS3 JK into floppy drive Note The floppy drive used to boot the system Drive A should be connected after the twist in the cable connector JS3 JK Plug hard drive data connector JS3 JH...

Страница 17: ...Unused Ext Floppy 1 Not installed Ide 3 Unused 127MB Custom Configuration System BIOS Setup Advanced Configuration C 2002 General Software Inc All rights reserved BIOS Extension Disabled COM1 03F8 Enabled IRQ IRQ4 DiskOnChip Disabled COM2 02F8 Enabled IRQ IRQ3 Parallel Port Mode SPP LPT1 0378 Enabled IRQ IRQ7 Display Type CRT PS 2 Mouse Enabled IRQ IRQ12 I O Register Base Address 0E0h PCI Int A IR...

Страница 18: ...ithout any files on it The DiskOnChip will appear as Drive D in systems with an installed hard drive If a hard drive is not installed the DOC will appear as Drive C 1 Boot your system under DOS or Windows if using Windows start a DOS session 2 Type SYS C or SYS D if appropriate 8 Configuration Operation EPM CPU 10 Reference Manual ...

Страница 19: ...orth Bridge and an I O Module South Bridge Dimensions are given below to help with pre production planning and layout CPU Module North Bridge I O Module South Bridge Overall Height Fan Fanless Model Figure 1 Dimensions Not to scale All dimensions in inches EPM CPU 10 Reference Manual Reference 9 ...

Страница 20: ...rectly to the underside of the EPM CPU 10 PC 104 expansion modules can be secured to the underside of the EPM CPU 10 however the 40 pin and 64 pin ISA feedthrough connectors may need to be extended and longer standoffs might need to be used to provide adequate clearance between the PCI connector and the components on the top side of the PC 104 module The entire assembly can sit on a table top or i...

Страница 21: ...External Connectors External Connectors CONNECTOR LOCATION DIAGRAMS Figure 3 Connector Location Diagram CPU Module Figure 4 Connector Location Diagram I O Module EPM CPU 10 Reference Manual Reference 11 ...

Страница 22: ...Logic VL CBL 4401 Contact Factory 32 JS1 Main Power Input Berg 69176 010 Housing Berg 47715 000 Pins VersaLogic VL CBL 1008 Interface from industry standard ATX power supply 18 JS2 PLD Reprogramming Port Factory use Only JS3 IDE0 Floppy General Purpose Input General Purpose Output NMI Robinson Nugent P50E 080S TG VersaLogic VL CBL 8002 Breakout to standard PC device connectors 14 JS4 Keyboard Mous...

Страница 23: ... Data 15A 8 Data bit 7 15B 7 Isolated Ground 16A 21 Ground 16B 8 Isolated Ground 17A 9 Data bit 8 17B 2 Transmit Data 18A 22 Ground 18B 1 Transmit Data 19A 10 Acknowledge 19B PBRESET Pushbutton Reset 20A 23 Ground 20B Ground 21A 11 Port Busy 21B COM1 1 Data Carrier Detect 22A 24 Ground 22B JF 6 Data Set Ready 23A 12 Paper End 23B 2 Receive Data 24A 25 Ground 24B 7 Request to Send 25A 13 Select 25B...

Страница 24: ...15 Data bit 1 15B 15 Ground 16A 16 Data bit 14 16B 16 Motor Enable 0 17A 17 Data bit 0 17B 17 Ground 18A 18 Data bit 15 18B 18 Direction Select 19A 19 Ground 19B 19 Ground 20A 20 No connection 20B 20 Motor Step 21A 21 No connection 21B 21 Ground 22A 22 Ground 22B 22 Write Data Strobe 23A 23 I O write 23B 23 Ground 24A 24 Ground 24B 24 Write Enable 25A 25 I O read 25B 25 Ground 26A 26 Ground 26B 26...

Страница 25: ...ock Locations Jumper Block Locations Note Jumpers shown in as shipped configuration Figure 5 Jumper Block Locations CPU Module Figure 6 Jumper Block Locations I O Module EPM CPU 10 Reference Manual Reference 15 ...

Страница 26: ...ut In In 4 800x600 Dual Scan STN Color In Out In Out 5 640x480 Sharp TFT Color In Out Out In 6 640x480 18 bit TFT Color In Out Out Out 7 1024x768 TFT Color Out In In In 8 800x600 TFT Color Out In In Out 9 800x600 TFT Color Out In Out In 10 800x600 TFT Color Out In Out Out 11 800x600 Dual Scan STN Color Out Out In In 12 800x600 Dual Scan STN Color Out Out In Out 13 1024x768 TFT Color Out Out Out In...

Страница 27: ... System BIOS is field upgradable using the BIOS upgrade utility See www versalogic com private jaguarsupport asp for further information In VS2 3 4 Video BIOS Selector In Primary Video BIOS Out Secondary Video BIOS Note The secondary System BIOS is field upgradable using the BIOS upgrade utility See www versalogic com private jaguarsupport asp for further information In VS2 5 6 General Purpose Jum...

Страница 28: ...power connectors be wired correctly Make sure to use all three 5VDC pins and all four ground pins to prevent excess voltage drop Table 6 Main Power Connector Pinout JS1 Pin Signal Name Description 1 Ground Ground 2 5VDC Power Input 3 Ground Ground 4 12VDC Power Input 5 Ground Ground 6 12VDC Power Input 7 3 3VDC Power Input 8 5VDC Power Input 9 Ground Digital Ground 10 5VDC Power Input Note The 3 3...

Страница 29: ...cally draw their power directly from the EPM CPU 10 and driving long RS 232 lines at high speed can increase power demand LITHIUM BATTERY Warning To prevent shorting premature failure or damage to the lithium battery do not place the unit on a conductive surface such as metal black conductive foam or the outside surface of a metalized ESD protective pouch The lithium battery may explode if mistrea...

Страница 30: ...not be covered under the board warranty PROCESSOR SIDE BUS SELECTION Pentium and Celeron CPU s normally select their Processor Side Bus Speed HEAT SINK A heat sink and cooling fan must be in place whenever power is applied to the CPU The fan connects to header JN1 for power Table 7 Fan Power Connector JN1 Pin Signal Name Function 1 5V Fan Power 2 GND Ground Note A fan is not required for the low p...

Страница 31: ...d period Once the throttling percentage is initialized in the CMOS Setup it can be enabled and disabled by writing to the Throttle control bit in the VersaLogic Special Control Register See page 41 This gives the user a very simple means to throttle back during a time of little activity and to re establish full power when needed The EPM CPU 10b Low Power Fanless and the EPM CPU 10e versions are 56...

Страница 32: ...in SODIMM memory module with the following characteristics Storage Capacity 32 to 256 MB Voltage 3 3 Volt Error Detection Not supported Error Correction Not supported Type EPM CPU 10d SDRAM PC 100 or faster EPM CPU 10b c e SDRAM PC 66 or faster 22 Reference EPM CPU 10 Reference Manual ...

Страница 33: ... CMOS Setup defaults This allows the system to boot up with user defined settings from cleared or corrupted CMOS RAM battery failure or battery less operation All CMOS setup defaults can be changed except the time and date Warning If the CMOS Setup defaults are set in a way that makes the system unbootable and unable for the user to enter CMOS Setup the EPM CPU 10 will need to be serviced by the f...

Страница 34: ...OC with pin 1 of socket U1 on the I O module 2 Push the DOC into the socket carefully until it is fully seated Warning The DOC will be permanently damaged if installed incorrectly When installing the DOC be sure to align pin 1 on the chip with pin 1 on the socket To prevent electrostatic damage first touch a grounded surface to discharge any static electricity from your body CMOS SETUP To enable t...

Страница 35: ... are no configuration jumpers for COM1 because it only operates in RS 232 mode Jumper VS3 is used to configure COM2 for RS 232 422 485 operation See page 16 and 17 for jumper configuration details COM2 RS 485 MODE LINE DRIVER CONTROL The TxD TxD differential line driver can be turned on and off by manipulating the DTR handshaking line The following code example shows how to turn the line driver fo...

Страница 36: ...tected with IEC 61000 4 2 Level 4 rated TVS components to help protect against ESD damage Table 8 Connectors JF JG Serial Port Pinout COM1 JS4 Pin COM2 JS4 Pin RS 232 RS 422 RS 485 JF JG DB9 Pin 21B 31B DCD 1 22B 32B DSR 6 23B 33B RXD TxD TxD 2 24B 34B RTS TxD TxD 7 25B 35B TXD 3 26B 36B CTS Ground Ground 8 27B 37B DTR RxD TxD RxD 4 28B 38B RI RxD TxD RxD 9 29B 39B Ground Ground Ground 5 30B 40B N...

Страница 37: ... protect against ESD damage Table 9 LPT1 Parallel Port Pinout JS4 Pin Centronics Signal Signal Direction JA Pin 1A Strobe Out 1 2A Auto feed Out 14 3A Data bit 1 In Out 2 4A Printer error In 15 5A Data bit 2 In Out 3 6A Reset Out 16 7A Data bit 3 In Out 4 8A Select input Out 17 9A Data bit 4 In Out 5 10A Ground 18 11A Data bit 5 In Out 6 12A Ground 19 13A Data bit 6 In Out 7 14A Ground 20 15A Data...

Страница 38: ...Data bit 3 11 12A HD12 DATA 12 Data bit 12 12 13A HD2 DATA 2 Data bit 2 13 14A HD13 DATA 13 Data bit 13 14 15A HD1 DATA 1 Data bit 1 15 16A HD14 DATA 14 Data bit 14 16 17A HD0 DATA 0 Data bit 0 17 18A HD15 DATA 15 Data bit 15 18 19A Ground Ground Ground 19 20A NC NC No connection 20 21A NC NC No connection 21 22A Ground Ground Ground 22 23A HWR HOST IOW I O write 23 24A Ground Ground Ground 24 25A...

Страница 39: ...otected 5V 4 38A Keyboard Data 1 39A Ground 3 40A Keyboard Clock 5 JB Mouse Connector JC Keyboard Connector PROGRAMMABLE LED The high density I O connector JS4 includes an output signal for attaching a software controlled LED Connect the cathode of the LED to JS4 28A anode to JS4 27A An on board resistor limits the current to 15 mA when the circuit is turned on To turn the LED on and off set or cl...

Страница 40: ...JK Warning Cable length must be 18 or less to maintain proper signal integrity The grounds in this connector should not be used to carry motor current Table 12 Floppy Disk Interface Connector Pinout JS3 Pin Signal Name Function JK JL Pin 1B Ground Ground 1 2B R LC Load Head 2 3B Ground Ground 3 4B NC No Connection 4 5B Ground Ground 5 6B NC No Connection 6 7B Ground Ground 7 8B INDX Beginning Of T...

Страница 41: ...IDEO OUTPUT CONNECTOR See the Connector Location Diagram on page 11 for pin and connector location information An adapter cable part number VL CBL 1007 is available to translate JN2 into a standard 15 pin D Sub SVGA connector This connector is protected with IEC 61000 4 2 Level 4 rated TVS components to help protect against ESD damage Table 14 Video Output Pinout JN2 Pin Signal Name Function Mini ...

Страница 42: ... FP8 LD7 G3 G0 SB2 FG0 B3 UG1 UB1 JN4 18 FP9 LD6 G4 G1 SB3 FG1 R4 UB1 LR1 JN4 19 FP10 LD5 G5 G2 SB4 FG2 G4 UR2 LG1 JN4 20 FP11 LD4 R0 G3 SB5 FG3 B4 UG2 LB1 JN4 21 FP12 LD3 R1 G4 FG0 SG0 R5 LG1 UR2 JN4 22 FP13 LD2 R2 G5 FG1 SG1 G5 LB1 UG2 JN4 23 FP14 LD1 R3 G6 FG2 SG2 B5 LR2 UB2 JN4 24 FP15 LD0 R4 G7 FG3 SG3 R6 LG2 LR2 JN4 25 FP16 R0 FG4 FR0 LG2 JN4 26 FP17 R1 FG5 FR1 LB2 JN4 27 FP18 R2 SG0 FR2 UR3...

Страница 43: ...1 Sharp LM64C35P NEC NL6448AC33 27 NEC NL6448AC33 18 NEC NL6448AC33 24 LG Elec LCA4VE02A LG Elec LP104S2 Samsung LT104V4 101 Hitachi TX31D27VC1CAB Hitachi TX26D80VC1CAA FLAT PANEL DISPLAY SELECTION The video BIOS shipped with the EPM CPU 10 supports up to 15 different flat panel configurations Use jumper block VN1 to select which type of panel is used and make sure to configure CMOS Setup to enabl...

Страница 44: ...S vendors ETHERNET CONNECTOR Table 16 RJ45 Ethernet Connector JS4 Pin Signal Name Function JE Pin 11B IGND Isolated Ground 4 12B IGND Isolated Ground 5 13B R Receive Data 6 14B R Receive Data 3 15B IGND Isolated Ground 7 16B IGND Isolated Ground 8 17B T Transmit Data 2 18B T Transmit Data 1 Ethernet Status LED D2 provides an onboard indication of the current condition of the board s Ethernet funct...

Страница 45: ...tchdog timer powers up and resets to a disabled state REFRESHING THE WATCHDOG If the watchdog timer is enabled software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire 1 0 sec minimum Outputting a 5Ah to the Watchdog Timer Hold Off Register at 0E1h or 1E1h resets the watchdog time out period see page 41 for additional information There is no provision ...

Страница 46: ...ith IEC 61000 4 2 Level 4 rated TVS components to help protect against ESD damage Table 17 USB 1 1 Interface Connector JS4 Pin Signal Name Function JD Pin 1B USBPWR1 5V Protected 1 2B GND Ground 6 3B USBP00 Channel 0 Data 2 4B GND1 Cable Shield 7 5B USBP01 Channel 0 Data 3 6B USBP11 Channel 1 Data 8 7B GND1 Cable Shield 4 8B USBP10 Channel 1 Data 9 9B GND Ground 5 10B USBPWR1 5V Protected 10 Warni...

Страница 47: ...es are stacked under the EPM CPU 10 under any PC 104 Plus modules 16 bit modules first followed by 8 bit PC 104 modules If necessary a 40 pin and 64 pin ISA feedthrough connector extender and long standoffs may need to be used to provide adequate clearance between the PCI connector and the components on the top side of the PC 104 module I O CONFIGURATION PC 104 Plus Modules No configuration is nec...

Страница 48: ... shadowed CMOS setup is used to enable or disable this feature Table 18 Memory Map Start Address End Address Comment E0000h FFFFFh System BIOS Flash Page BIOS Ext D0000h DFFFFh PC 104 and DOC C0000h CFFFFh Video BIOS A0000h BFFFFh Video RAM 00000h 9FFFFh System DRAM Note The memory region from E0000h EFFFFh is controlled by the Map and Paging Control Register 38 Reference EPM CPU 10 Reference Manu...

Страница 49: ...e Standard I O Addresses Alternate I O Addresses Special Control Register 0E0h 1E0h Watchdog Hold Off Register Revision Indicator 0E1h 1E1h Special Control Register 0E2h 1E2h Map and Paging Control Register 0E3h 1E3h Primary Hard Drive Controller 1F0h 1F7h COM2 Serial Port 2F8h 2FFh LPT1 Parallel Port 378h 37Fh SVGA Video 3B0h 3DFh Floppy Disk Controller 3F0h 3F7h COM1 Serial Port 3F8h 3FFh User s...

Страница 50: ...ation jumpers All configuration is handled through CMOS setup The switches in the diagram below indicate the various CMOS Setup options Closed switches show factory default settings The temperature monitor interrupt and watchdog interrupt are enabled disabled with the Special Control Register Note If your design needs to use interrupt lines on the PC 104 bus we recommend using IRQ5 IRQ9 and or IRQ...

Страница 51: ...GPI 0 Logic High GPI 1 Logic Low Note This bit is a read only bit D4 GPO General Purpose Output Controls TTL output at JS3 37B GPO 0 Logic High GPO 1 Logic Low D3 HDOGNMI Non Maskable Interrupt Enable Controls the generation of Non Maskable Interrupts whenever the CPU temperature sensor detects an over temperature condition HDOGNMI 0 Disable HDOGNMI 1 Enable D2 WDOGSTA WDOG STATUS Indicates if the...

Страница 52: ...r codes are reserved for future products PC4 PC3 PC2 PC1 PC0 Product Code 0 0 0 1 0 EPM CPU 10 Note This bits are read only D2 TCO Throttling Code This bit specifies how throttling is enabled at power up and reset 0 EPM CPU 10c No Throttling EPM CPU 10d 1 EPM CPU 10b Throttling set at 37 5 EPM CPU 10e Note This bit is read only D1 D0 REV1 REV0 Revision Level These bits are representative of the EP...

Страница 53: ...sets the watchdog timeout period preventing the CPU from being reset or generation of NMI for the next 1 second Special Control Register SCR READ WRITE 00E2h or 01E2h via CMOS setup D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved JPI Throttle Table 21 Special Control Register Bit Assignments Bit Mnemonic Description D7 D2 Reserved Reserved These bits have no function ...

Страница 54: ...00 0 1 0 D800 0 1 1 DE00 0 D4 SB SEL System BIOS Selection Indicates the status of jumper VS2 1 2 SB SEL 0 Jumper out Secondary System BIOS selected SB SEL 1 Jumper in Primary System BIOS selected Note This is a read only bit D3 VB SEL Video BIOS Selection Indicates the status of jumper VS2 3 4 VB SEL 0 Jumper out Secondary System BIOS selected VB SEL 1 Jumper in Primary System BIOS selected Note ...

Страница 55: ...es www asiliant com 690X0 Disk On Chip M Systems Inc www m sys com DOC2000 PC 104 Specification PC 104 Consortium www controlled com pc104 PC 104 Resource Guide PC 104 Plus Specification VersaLogic Corp www versalogic com PC 104 Resource Guide CPU Chips Celeron Intel Corporation www developer intel com Pentium III General PC Documentation Microsoft Press mspress microsoft com The Programmer s PC S...

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