
Watchdog Timer
Watchdog Timer
A watchdog timer circuit is included on the EPM-CPU-10 to reset the CPU or issue a NMI if
proper software execution fails or a hardware malfunction occurs.
E
NABLING THE
W
ATCHDOG
To enable or disable the watchdog to reset the CPU, set or clear bit D0 in I/O port 0E0h (or
1E0h). When changing the contents of the register, make sure not to alter the value of the other
bits. It is recommend to refresh the watchdog prior to enabling or disabling the watchdog.
The following code example enables the watchdog reset:
in
al,E0h
or
al,01h
out E0h,al
To enable or disable the watchdog to issue an NMI, set or clear bit D1 in I/O per 0E0h (or 1E0h).
When charging the contents of the register, make sure not to alter the value of the other bits. It is
recommend to refresh the watchdog prior to enabling or disabling the watchdog. Bit D2 can be
read to determine if watchdog timer has expired.
The following code example enables the watchdog NMI:
in
al,E0h
or
al,02h
out E0h,al
Note!
The watchdog timer powers up and resets to a disabled state.
R
EFRESHING THE
W
ATCHDOG
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (1.0 sec minimum). Outputting a 5Ah to the Watchdog Timer
Hold-Off Register at 0E1h (or 1E1h) resets the watchdog time-out period, see page 41 for
additional information.
There is no provision for selecting a different timeout period using software.
The following code example refreshes the watchdog:
mov al,5Ah
out E1h,al
CPU Temperature Monitor
A thermometer circuit is located directly under the CPU chip which constantly monitors the case
temperature of the CPU. This circuit can be used to detect over-temperature conditions which can
result from fan or heat sink failure or excessive ambient temperatures.
CMOS Setup is used to set the temperature detection threshold. A status bit in the Special Control
Register can be read to determine if the case temperature is above or below the threshold.
The system can be configured to generate a Non-Maskable Interrupt (NMI) when the temperature
exceeds the threshold.
See page 41 for additional information.
EPM-CPU-10 Reference Manual
Reference – 35