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Figure 3-III Edge Gating: Signal S1 on input 8 triggers the edge gate
to open, when an active edge is detected. Only pulses with their
active edge within the gate are being tagged
Level Gating
The Level Gate trigger is located on input 9. When the signal on input 9 is higher than the specified
threshold voltage, tags are processed normally. When it is lower, the input signals are ignored.
Please note that the level gate signal has in internal jitter of 5 ns.
Disclaimer: Level gate starts 25ns before the trigger signal.
Figure 3-IV
Level Gating:
When Signal S1 on input 9 is higher than the
threshold voltage, it triggers the level gate open. Gate width is the same
as the high time of S1. Only pulses with their active edge within the gate
are being tagged. Note: there is an offset of
∼
25 ns between when the
level gate starts and when trigger input is tagged.
