SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26
Design-in
Page 166 of 217
LQG15HN39NJ02) should be implemented at the antenna port as described in Figure 59, Figure 60 and
Figure 61, as implemented in the EMC / ESD approved reference design of SARA-U2 modules
The antenna interface application circuit implemented in the EMC / ESD approved reference designs of SARA-G3
and SARA-U2 series modules is described in Figure 59 when an antenna detection circuit is not implemented,
and is described in Figure 60 and Table 39 when an antenna detection circuit is implemented (section 2.4).
RESET_N pin
The following precautions are suggested for the
RESET_N
line of SARA-G3 and SARA-U2 series modules,
depending on the application board handling, to satisfy ESD immunity test requirements:
It is recommended to keep the connection line to
RESET_N
as short as possible
Maximum ESD sensitivity rating of the
RESET_N
pin is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if the
RESET_N
pin is externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the
RESET_N
line, close to accessible point
The
RESET_N
application circuit implemented in the EMC / ESD approved reference design of SARA-G3 modules
is described in Figure 53 and Table 34 (section 2.3.2).
SIM interface
The following precautions are suggested for SARA-G3 and SARA-U2 modules SIM interface (
VSIM
,
SIM_RST
,
SIM_IO
,
SIM_CLK
), depending on the application board handling, to satisfy ESD immunity test requirements:
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines connected to
VSIM
,
SIM_RST
,
SIM_IO
and
SIM_CLK
pins to assure SIM interface functionality when an electrostatic
discharge is applied to the application board enclosure
It is suggested to use as short as possible connection lines at the SIM pins
Maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if SIM interface pins are externally accessible on the application board.
The following precautions are suggested to achieve higher protection level:
A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140) should
be mounted on each SIM interface line, close to accessible points (i.e. close to the SIM card holder)
The SIM interface application circuit implemented in the EMC / ESD approved reference design of SARA-G3
modules is described in Figure 64 and Table 42 (section 2.5).
Other pins and interfaces
All the module pins that are externally accessible on the device integrating SARA-G3 and SARA-U2 series module
should be included in the ESD immunity test since they are considered to be a port as defined in
ETSI EN 301
489-1
[20]. Depending on applicability, to satisfy ESD immunity test requirements according to ESD category
level, all the module pins that are externally accessible should be protected up to ±4 kV for direct Contact
Discharge and up to ±8 kV for Air Discharge applied to the enclosure surface.
The maximum ESD sensitivity rating of all the other pins of the module is 1 kV (Human Body Model according to
JESD22-A114). Higher protection level could be required if the related pin is externally accessible on the
application board. The following precautions are suggested to achieve higher protection level:
A very low capacitance (i.e. less or equal to 1 pF) ESD protection device (e.g. Tyco Electronics PESD0402-140)
should be mounted on each high speed USB line, close to accessible points (i.e. close to the USB connector)
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG or EPCOS CT0402S14AHSG varistor)
should be mounted on each generic interface line, close to accessible point
