SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26
Design-in
Page 139 of 217
If only
TXD
and
RXD
lines are provided, data delivered by the DTE can be lost with these settings:
o
HW flow-control enabled in the module (AT&K3, that is the default setting)
o
Module power saving enabled by AT+UPSV=1
o
HW flow-control disabled in the DTE
In this case the first character sent when the module is in idle mode will be a wake-up character and will
not be a valid communication character (see section 1.9.1.4 for the complete description).
If power saving is enabled the application circuit with the
TXD
and
RXD
lines only is not recommended.
During command mode the DTE must send to the module a wake-up character or a dummy “AT” before
each command line (see section 1.9.1.4 for the complete description), but during data mode the wake-up
character or the dummy “AT” would affect the data communication.
Additional considerations
If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the
apposite 1.8 V input of the module (DCE) can be implemented, as an alternative low-cost solution, by means of
an appropriate voltage divider. Consider the value of the pull-up integrated at the input of the module (DCE) for
the correct selection of the voltage divider resistance values and mind that any DTE signal connected to the
module must be tri-stated or set low when the module is in power-down mode and during the module power-
on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits
and allow a proper boot of the module (see the remark below).
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the apposite 3.0 V input of
the Application Processor (DTE) can be implemented by means of an appropriate low-cost non-inverting buffer
with open drain output. The non-inverting buffer should be supplied by the
V_INT
supply output of the cellular
module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate required
by the application for the appropriate selection of the resistance value for the external pull-up biased by the
application processor supply rail.
If the USB interface of SARA-U2 modules is connected to the host application processor, the UART can be
left unconnected as not required for AT and data communication, but it is anyway highly recommended
to provide direct access to the
TXD
,
RXD
,
RTS
,
CTS
pins of SARA-U2 modules for the execution of
firmware upgrade over UART using the u-blox EasyFlash tool and for diagnostic purposes: provide a test-
point on each line to accommodate the access and provide a 0
series resistor on each line to detach the
module pin from any other connected device.
Any external signal connected to the UART interface must be tri-stated or set low when the module is in
power-down mode and during the module power-on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module. If the
external signals connected to the cellular module cannot be tri-stated or set low, insert a multi-channel
digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the
two-circuit connections and set to high impedance during module power down mode and during the
module power-on sequence.
The ESD sensitivity rating of UART interface pins is 1 kV (Human Body Model according to JESD22-A114).
A higher protection level could be required if the lines are externally accessible on the application board.
This higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
2.6.1.2
Guidelines for UART layout design
The UART
serial interface requires the same consideration regarding electro-magnetic interference as any other
digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the
signals can cause the radiation of some harmonics of the digital data frequency.
