SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26
Design-in
Page 158 of 217
Figure 87 describes an application circuit example for connecting the I
2
S digital audio interface of SARA-G340,
SARA-G350 and SARA-U2 modules to an external audio voice codec, using the same parts listed in Table 57.
The module’s I
2
S interface (I
2
S master) is connected to the related pins of the external audio codec (I
2
S slave).
The
V_INT
output supplies the external audio codec, defining proper digital interfaces voltage level.
The external audio codec is controlled by the application processor using the DDC (I
2
C) interface.
The clock output of the application processor is connected to the clock input of the external audio codec to
provide clock reference.
Additional components are provided for EMC and ESD immunity conformity: a 10 nF bypass capacitor and a
series chip ferrite bead noise/EMI suppression filter provided on each microphone line input and speaker line
output of the external codec as described in Figure 87 and Table 57. The necessity of these or other
additional parts for EMC improvement may depend on the specific application board design.
R2
R1
GND
U1
SARA-G340 / SARA-G350
SARA-U2 series
Audio
Codec
SDA
SCL
SDA
SCL
Clock Output
MCLK
GND
R3
C3
C2
C1
4
V_INT
VDD
1V8
MICBIAS
C4
R4
C5
C6
EMI1
MICLN
MICLP
Microphone
Connector
EMI2
MIC
C12 C11
J1
MICGND
R5
C8
C7
SPK
Speaker
Connector
OUTP
OUTN
J2
C10 C9
C14 C13
EMI3
EMI4
IRQn
BCLK
LRCLK
SDIN
SDOUT
36
I2S_CLK
34
I2S_WA
35
I2S_TXD
37
I2S_RXD
1V8
1V8
Application Processor
GND
AT interface
D3
D1
D4
D2
0
Ω
0
Ω
TP
TP
0
Ω
0
Ω
TP
TP
Figure 87: Application circuit for connecting SARA-G3 / SARA-U2 modules with an external audio codec
Any external signal connected to the I
2
S interface must be tri-stated or set low when the module is in
power-down mode and during the module power-on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module. If the
external signals connected to the cellular module cannot be tri-stated or set low, insert a multi-channel
digital switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections
and set to high impedance during module power down mode and power-on sequence.
The ESD sensitivity rating of I
2
S interface pins is 1 kV (Human Body Model according to JESD22-A114). A
higher protection level could be required if the lines are externally accessible on the application board. A
higher protection level can be achieved by mounting a general purpose ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
It is highly recommended to provide direct access to the I
2
S pins of SARA-G3 modules product versions
“02” onwards for diagnostic purposes: provide a test-point on each line to accommodate the access and
provide a 0
series resistor on each line to detach the module pin from any other connected device.
If the I
2
S pins are not used, they can be left unconnected on the application board, but test-points
connected to the I
2
S pins of SARA-G3 modules product versions “02” onwards are highly recommended.
2.7.2.2
Guidelines for digital audio layout design
The I
2
S digital audio interface lines require the same considerations regarding electromagnetic interference as
any other digital interface. Keep the traces short and avoid coupling with RF lines / parts or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.
